| locore.S (292900) | locore.S (292903) |
|---|---|
| 1/*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 9 unchanged lines hidden (view full) --- 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 9 unchanged lines hidden (view full) --- 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/powerpc/booke/locore.S 292900 2015-12-30 02:23:14Z jhibbits $ | 26 * $FreeBSD: head/sys/powerpc/booke/locore.S 292903 2015-12-30 03:43:25Z jhibbits $ |
| 27 */ 28 29#include "assym.s" 30 31#include "opt_hwpmc_hooks.h" 32 33#include <machine/asm.h> 34#include <machine/hid.h> --- 261 unchanged lines hidden (view full) --- 296 bl 1f 297 298 .globl bp_ntlb1s 299bp_ntlb1s: 300 .long 0 301 302 .globl bp_tlb1 303bp_tlb1: | 27 */ 28 29#include "assym.s" 30 31#include "opt_hwpmc_hooks.h" 32 33#include <machine/asm.h> 34#include <machine/hid.h> --- 261 unchanged lines hidden (view full) --- 296 bl 1f 297 298 .globl bp_ntlb1s 299bp_ntlb1s: 300 .long 0 301 302 .globl bp_tlb1 303bp_tlb1: |
| 304 .space 4 * 3 * 16 | 304 .space 4 * 3 * 64 |
| 305 306 .globl bp_tlb1_end 307bp_tlb1_end: 308 309/* 310 * Initial configuration 311 */ 3121: mflr %r31 /* r31 hold the address of bp_ntlb1s */ --- 413 unchanged lines hidden (view full) --- 726 oris %r3, %r3, (L1CSR1_ICPE | L1CSR1_ICE)@h 727 ori %r3, %r3, (L1CSR1_ICPE | L1CSR1_ICE)@l 728 isync 729 mtspr SPR_L1CSR1, %r3 730 isync 731 blr 732 733/* | 305 306 .globl bp_tlb1_end 307bp_tlb1_end: 308 309/* 310 * Initial configuration 311 */ 3121: mflr %r31 /* r31 hold the address of bp_ntlb1s */ --- 413 unchanged lines hidden (view full) --- 726 oris %r3, %r3, (L1CSR1_ICPE | L1CSR1_ICE)@h 727 ori %r3, %r3, (L1CSR1_ICPE | L1CSR1_ICE)@l 728 isync 729 mtspr SPR_L1CSR1, %r3 730 isync 731 blr 732 733/* |
| 734 * L2 cache disable/enable/inval sequences for E500mc. 735 */ 736 737ENTRY(l2cache_inval) 738 mfspr %r3, SPR_L2CSR0 739 oris %r3, %r3, (L2CSR0_L2FI | L2CSR0_L2LFC)@h 740 ori %r3, %r3, (L2CSR0_L2FI | L2CSR0_L2LFC)@l 741 isync 742 mtspr SPR_L2CSR0, %r3 743 isync 7441: mfspr %r3, SPR_L2CSR0 745 andis. %r3, %r3, L2CSR0_L2FI@h 746 bne 1b 747 blr 748 749ENTRY(l2cache_enable) 750 mfspr %r3, SPR_L2CSR0 751 oris %r3, %r3, (L2CSR0_L2E | L2CSR0_L2PE)@h 752 isync 753 mtspr SPR_L2CSR0, %r3 754 isync 755 blr 756 757/* 758 * Branch predictor setup. 759 */ 760ENTRY(bpred_enable) 761 mfspr %r3, SPR_BUCSR 762 ori %r3, %r3, BUCSR_BBFI 763 isync 764 mtspr SPR_BUCSR, %r3 765 isync 766 ori %r3, %r3, BUCSR_BPEN 767 isync 768 mtspr SPR_BUCSR, %r3 769 isync 770 blr 771 772ENTRY(dataloss_erratum_access) 773 /* Lock two cache lines into I-Cache */ 774 sync 775 mfspr %r11, SPR_L1CSR1 776 rlwinm %r11, %r11, 0, ~L1CSR1_ICUL 777 sync 778 isync 779 mtspr SPR_L1CSR1, %r11 780 isync 781 782 mflr %r9 783 bl 1f 784 .long 2f-. 7851: 786 mflr %r5 787 lwz %r8, 0(%r5) 788 mtlr %r9 789 add %r8, %r8, %r5 790 icbtls 0, 0, %r8 791 addi %r9, %r8, 64 792 793 sync 794 mfspr %r11, SPR_L1CSR1 7953: andi. %r11, %r11, L1CSR1_ICUL 796 bne 3b 797 798 icbtls 0, 0, %r9 799 800 sync 801 mfspr %r11, SPR_L1CSR1 8023: andi. %r11, %r11, L1CSR1_ICUL 803 bne 3b 804 805 b 2f 806 .align 6 807 /* Inside a locked cacheline, wait a while, write, then wait a while */ 8082: sync 809 810 mfspr %r5, TBR_TBL 8114: addis %r11, %r5, 0x100000@h /* wait around one million timebase ticks */ 812 mfspr %r5, TBR_TBL 813 subf. %r5, %r5, %r11 814 bgt 4b 815 816 stw %r4, 0(%r3) 817 818 mfspr %r5, TBR_TBL 8194: addis %r11, %r5, 0x100000@h /* wait around one million timebase ticks */ 820 mfspr %r5, TBR_TBL 821 subf. %r5, %r5, %r11 822 bgt 4b 823 824 sync 825 826 /* 827 * Fill out the rest of this cache line and the next with nops, 828 * to ensure that nothing outside the locked area will be 829 * fetched due to a branch. 830 */ 831 .rept 19 832 nop 833 .endr 834 835 icblc 0, 0, %r8 836 icblc 0, 0, %r9 837 838 blr 839 840/* |
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| 734 * int setfault() 735 * 736 * Similar to setjmp to setup for handling faults on accesses to user memory. 737 * Any routine using this may only call bcopy, either the form below, 738 * or the (currently used) C code optimized, so it doesn't use any non-volatile 739 * registers. 740 */ 741 .globl setfault --- 36 unchanged lines hidden --- | 841 * int setfault() 842 * 843 * Similar to setjmp to setup for handling faults on accesses to user memory. 844 * Any routine using this may only call bcopy, either the form below, 845 * or the (currently used) C code optimized, so it doesn't use any non-volatile 846 * registers. 847 */ 848 .globl setfault --- 36 unchanged lines hidden --- |