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booke_machdep.c (236141) booke_machdep.c (236324)
1/*-
1/*-
2 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
2 * Copyright (C) 2006-2012 Semihalf
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

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74 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
75 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
76 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
77 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
78 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
79 */
80
81#include <sys/cdefs.h>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

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74 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
75 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
76 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
77 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
78 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
79 */
80
81#include <sys/cdefs.h>
82__FBSDID("$FreeBSD: head/sys/powerpc/booke/machdep.c 236141 2012-05-27 10:25:20Z raj $");
82__FBSDID("$FreeBSD: head/sys/powerpc/booke/machdep.c 236324 2012-05-30 17:34:40Z raj $");
83
84#include "opt_compat.h"
85#include "opt_ddb.h"
86#include "opt_kstack_pages.h"
87#include "opt_platform.h"
88
89#include <sys/cdefs.h>
90#include <sys/types.h>

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124#include <machine/vmparam.h>
125#include <machine/spr.h>
126#include <machine/hid.h>
127#include <machine/psl.h>
128#include <machine/trap.h>
129#include <machine/md_var.h>
130#include <machine/mmuvar.h>
131#include <machine/sigframe.h>
83
84#include "opt_compat.h"
85#include "opt_ddb.h"
86#include "opt_kstack_pages.h"
87#include "opt_platform.h"
88
89#include <sys/cdefs.h>
90#include <sys/types.h>

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124#include <machine/vmparam.h>
125#include <machine/spr.h>
126#include <machine/hid.h>
127#include <machine/psl.h>
128#include <machine/trap.h>
129#include <machine/md_var.h>
130#include <machine/mmuvar.h>
131#include <machine/sigframe.h>
132#include <machine/machdep.h>
132#include <machine/metadata.h>
133#include <machine/platform.h>
134
135#include <sys/linker.h>
136#include <sys/reboot.h>
137
138#include <dev/fdt/fdt_common.h>
139#include <dev/ofw/openfirm.h>
140
133#include <machine/metadata.h>
134#include <machine/platform.h>
135
136#include <sys/linker.h>
137#include <sys/reboot.h>
138
139#include <dev/fdt/fdt_common.h>
140#include <dev/ofw/openfirm.h>
141
141#include <powerpc/mpc85xx/mpc85xx.h>
142
143#ifdef DDB
144extern vm_offset_t ksym_start, ksym_end;
145#endif
146
147#ifdef DEBUG
148#define debugf(fmt, args...) printf(fmt, ##args)
149#else
150#define debugf(fmt, args...)
151#endif
152
153extern unsigned char kernel_text[];
154extern unsigned char _etext[];
155extern unsigned char _edata[];
156extern unsigned char __bss_start[];
157extern unsigned char __sbss_start[];
158extern unsigned char __sbss_end[];
159extern unsigned char _end[];
160
142#ifdef DDB
143extern vm_offset_t ksym_start, ksym_end;
144#endif
145
146#ifdef DEBUG
147#define debugf(fmt, args...) printf(fmt, ##args)
148#else
149#define debugf(fmt, args...)
150#endif
151
152extern unsigned char kernel_text[];
153extern unsigned char _etext[];
154extern unsigned char _edata[];
155extern unsigned char __bss_start[];
156extern unsigned char __sbss_start[];
157extern unsigned char __sbss_end[];
158extern unsigned char _end[];
159
161extern void dcache_enable(void);
162extern void dcache_inval(void);
163extern void icache_enable(void);
164extern void icache_inval(void);
165
166/*
167 * Bootinfo is passed to us by legacy loaders. Save the address of the
168 * structure to handle backward compatibility.
169 */
170uint32_t *bootinfo;
171
172struct kva_md_info kmi;
173struct pcpu __pcpu[MAXCPU];

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281}
282
283u_int
284booke_init(uint32_t arg1, uint32_t arg2)
285{
286 struct pcpu *pc;
287 void *kmdp, *mdp;
288 vm_offset_t dtbp, end;
160/*
161 * Bootinfo is passed to us by legacy loaders. Save the address of the
162 * structure to handle backward compatibility.
163 */
164uint32_t *bootinfo;
165
166struct kva_md_info kmi;
167struct pcpu __pcpu[MAXCPU];

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275}
276
277u_int
278booke_init(uint32_t arg1, uint32_t arg2)
279{
280 struct pcpu *pc;
281 void *kmdp, *mdp;
282 vm_offset_t dtbp, end;
289 uint32_t csr;
290
291 kmdp = NULL;
292
293 end = (uintptr_t)_end;
294 dtbp = (vm_offset_t)NULL;
295
296 /*
297 * Handle the various ways we can get loaded and started:

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354
355 if (OF_init((void *)dtbp) != 0)
356 while (1);
357
358 if (fdt_immr_addr(CCSRBAR_VA) != 0)
359 while (1);
360
361 OF_interpret("perform-fixup", 0);
283
284 kmdp = NULL;
285
286 end = (uintptr_t)_end;
287 dtbp = (vm_offset_t)NULL;
288
289 /*
290 * Handle the various ways we can get loaded and started:

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347
348 if (OF_init((void *)dtbp) != 0)
349 while (1);
350
351 if (fdt_immr_addr(CCSRBAR_VA) != 0)
352 while (1);
353
354 OF_interpret("perform-fixup", 0);
355
356 /* Set up TLB initially */
357 booke_init_tlb(fdt_immr_pa);
362
358
363 /* Initialize TLB1 handling */
364 tlb1_init(fdt_immr_pa);
365
366 /* Reset Time Base */
367 mttb(0);
368
369 /* Init params/tunables that can be overridden by the loader. */
370 init_param1();
371
372 /* Start initializing proc0 and thread0. */
373 proc_linkup0(&proc0, &thread0);

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391 debugf(" end = 0x%08x\n", (u_int32_t)end);
392 debugf(" boothowto = 0x%08x\n", boothowto);
393 debugf(" kernel ccsrbar = 0x%08x\n", CCSRBAR_VA);
394 debugf(" MSR = 0x%08x\n", mfmsr());
395#if defined(BOOKE_E500)
396 debugf(" HID0 = 0x%08x\n", mfspr(SPR_HID0));
397 debugf(" HID1 = 0x%08x\n", mfspr(SPR_HID1));
398 debugf(" BUCSR = 0x%08x\n", mfspr(SPR_BUCSR));
359 /* Reset Time Base */
360 mttb(0);
361
362 /* Init params/tunables that can be overridden by the loader. */
363 init_param1();
364
365 /* Start initializing proc0 and thread0. */
366 proc_linkup0(&proc0, &thread0);

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384 debugf(" end = 0x%08x\n", (u_int32_t)end);
385 debugf(" boothowto = 0x%08x\n", boothowto);
386 debugf(" kernel ccsrbar = 0x%08x\n", CCSRBAR_VA);
387 debugf(" MSR = 0x%08x\n", mfmsr());
388#if defined(BOOKE_E500)
389 debugf(" HID0 = 0x%08x\n", mfspr(SPR_HID0));
390 debugf(" HID1 = 0x%08x\n", mfspr(SPR_HID1));
391 debugf(" BUCSR = 0x%08x\n", mfspr(SPR_BUCSR));
399
400 __asm __volatile("msync; isync");
401 csr = ccsr_read4(OCP85XX_L2CTL);
402 debugf(" L2CTL = 0x%08x\n", csr);
403#endif
404
405 debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp);
406
407 print_kernel_section_addr();
408 print_kenv();
409#if defined(BOOKE_E500)
410 //tlb1_print_entries();

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442
443 /* Initialise the message buffer. */
444 msgbufinit(msgbufp, msgbufsize);
445
446 /* Enable Machine Check interrupt. */
447 mtmsr(mfmsr() | PSL_ME);
448 isync();
449
392#endif
393
394 debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp);
395
396 print_kernel_section_addr();
397 print_kenv();
398#if defined(BOOKE_E500)
399 //tlb1_print_entries();

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431
432 /* Initialise the message buffer. */
433 msgbufinit(msgbufp, msgbufsize);
434
435 /* Enable Machine Check interrupt. */
436 mtmsr(mfmsr() | PSL_ME);
437 isync();
438
450 /* Enable D-cache if applicable */
451 csr = mfspr(SPR_L1CSR0);
452 if ((csr & L1CSR0_DCE) == 0) {
453 dcache_inval();
454 dcache_enable();
455 }
439 /* Enable L1 caches */
440 booke_enable_l1_cache();
456
441
457 csr = mfspr(SPR_L1CSR0);
458 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0)
459 printf("L1 D-cache %sabled\n",
460 (csr & L1CSR0_DCE) ? "en" : "dis");
461
462 /* Enable L1 I-cache if applicable. */
463 csr = mfspr(SPR_L1CSR1);
464 if ((csr & L1CSR1_ICE) == 0) {
465 icache_inval();
466 icache_enable();
467 }
468
469 csr = mfspr(SPR_L1CSR1);
470 if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0)
471 printf("L1 I-cache %sabled\n",
472 (csr & L1CSR1_ICE) ? "en" : "dis");
473
474 debugf("%s: SP = 0x%08x\n", __func__,
475 ((uintptr_t)thread0.td_pcb - 16) & ~15);
476
477 return (((uintptr_t)thread0.td_pcb - 16) & ~15);
478}
479
480#define RES_GRANULE 32
481extern uint32_t tlb0_miss_locks[];

--- 159 unchanged lines hidden --- 		442 debugf("%s: SP = 0x%08x\n", __func__,
443 ((uintptr_t)thread0.td_pcb - 16) & ~15);
444
445 return (((uintptr_t)thread0.td_pcb - 16) & ~15);
446}
447
448#define RES_GRANULE 32
449extern uint32_t tlb0_miss_locks[];

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