| mp_cpudep.c (257175) | mp_cpudep.c (259284) |
|---|---|
| 1/*- 2 * Copyright (c) 2008 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * --- 11 unchanged lines hidden (view full) --- 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2008 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * --- 11 unchanged lines hidden (view full) --- 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> |
| 28__FBSDID("$FreeBSD: head/sys/powerpc/aim/mp_cpudep.c 257175 2013-10-26 17:54:31Z nwhitehorn $"); | 28__FBSDID("$FreeBSD: head/sys/powerpc/aim/mp_cpudep.c 259284 2013-12-13 02:37:35Z jhibbits $"); |
| 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/kernel.h> 33#include <sys/bus.h> 34#include <sys/pcpu.h> 35#include <sys/proc.h> 36#include <sys/smp.h> --- 280 unchanged lines hidden (view full) --- 317 318 mtspr(SPR_CELL_TSCR, bsp_state[4]); 319 } 320 #endif 321 322 mtspr(SPR_CELL_TSRL, bsp_state[5]); 323 324 break; | 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/kernel.h> 33#include <sys/bus.h> 34#include <sys/pcpu.h> 35#include <sys/proc.h> 36#include <sys/smp.h> --- 280 unchanged lines hidden (view full) --- 317 318 mtspr(SPR_CELL_TSCR, bsp_state[4]); 319 } 320 #endif 321 322 mtspr(SPR_CELL_TSRL, bsp_state[5]); 323 324 break; |
| 325 case MPC7450: 326 case MPC7455: 327 case MPC7457: 328 /* Only MPC745x CPUs have an L3 cache. */ 329 reg = mpc745x_l3_enable(bsp_state[3]); 330 331 /* Fallthrough */ | |
| 332 case MPC7400: 333 case MPC7410: 334 case MPC7447A: 335 case MPC7448: | 325 case MPC7400: 326 case MPC7410: 327 case MPC7447A: 328 case MPC7448: |
| 329 case MPC7450: 330 case MPC7455: 331 case MPC7457: |
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| 336 /* XXX: Program the CPU ID into PIR */ 337 __asm __volatile("mtspr 1023,%0" :: "r"(PCPU_GET(cpuid))); 338 339 powerpc_sync(); 340 isync(); 341 342 mtspr(SPR_HID0, bsp_state[0]); isync(); 343 mtspr(SPR_HID1, bsp_state[1]); isync(); 344 | 332 /* XXX: Program the CPU ID into PIR */ 333 __asm __volatile("mtspr 1023,%0" :: "r"(PCPU_GET(cpuid))); 334 335 powerpc_sync(); 336 isync(); 337 338 mtspr(SPR_HID0, bsp_state[0]); isync(); 339 mtspr(SPR_HID1, bsp_state[1]); isync(); 340 |
| 341 /* Now enable the L3 cache. */ 342 switch (vers) { 343 case MPC7450: 344 case MPC7455: 345 case MPC7457: 346 /* Only MPC745x CPUs have an L3 cache. */ 347 reg = mpc745x_l3_enable(bsp_state[3]); 348 default: 349 break; 350 } 351 |
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| 345 reg = mpc74xx_l2_enable(bsp_state[2]); 346 reg = mpc74xx_l1d_enable(); 347 reg = mpc74xx_l1i_enable(); 348 349 break; 350 default: 351#ifdef __powerpc64__ 352 if (!(mfmsr() & PSL_HV)) /* Rely on HV to have set things up */ 353 break; 354#endif 355 printf("WARNING: Unknown CPU type. Cache performace may be " 356 "suboptimal.\n"); 357 break; 358 } 359} 360 | 352 reg = mpc74xx_l2_enable(bsp_state[2]); 353 reg = mpc74xx_l1d_enable(); 354 reg = mpc74xx_l1i_enable(); 355 356 break; 357 default: 358#ifdef __powerpc64__ 359 if (!(mfmsr() & PSL_HV)) /* Rely on HV to have set things up */ 360 break; 361#endif 362 printf("WARNING: Unknown CPU type. Cache performace may be " 363 "suboptimal.\n"); 364 break; 365 } 366} 367 |