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aim_machdep.c (258696) aim_machdep.c (261309)
1/*-
2 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
3 * Copyright (C) 1995, 1996 TooLs GmbH.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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50 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
51 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
52 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
53 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $
55 */
56
57#include <sys/cdefs.h>
1/*-
2 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
3 * Copyright (C) 1995, 1996 TooLs GmbH.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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50 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
51 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
52 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
53 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $
55 */
56
57#include <sys/cdefs.h>
58__FBSDID("$FreeBSD: head/sys/powerpc/aim/machdep.c 258696 2013-11-27 22:01:09Z nwhitehorn $");
58__FBSDID("$FreeBSD: head/sys/powerpc/aim/machdep.c 261309 2014-01-31 03:55:34Z jhibbits $");
59
60#include "opt_compat.h"
61#include "opt_ddb.h"
62#include "opt_kstack_pages.h"
63#include "opt_platform.h"
64
65#include <sys/param.h>
66#include <sys/proc.h>

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137#ifdef __powerpc64__
138extern int n_slbs;
139int cacheline_size = 128;
140#else
141int cacheline_size = 32;
142#endif
143int hw_direct_map = 1;
144
59
60#include "opt_compat.h"
61#include "opt_ddb.h"
62#include "opt_kstack_pages.h"
63#include "opt_platform.h"
64
65#include <sys/param.h>
66#include <sys/proc.h>

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137#ifdef __powerpc64__
138extern int n_slbs;
139int cacheline_size = 128;
140#else
141int cacheline_size = 32;
142#endif
143int hw_direct_map = 1;
144
145extern void *ap_pcpu;
146
145struct pcpu __pcpu[MAXCPU];
146
147static struct trapframe frame0;
148
149char machine[] = "powerpc";
150SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "");
151
152static void cpu_startup(void *);

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230#ifndef __powerpc64__
231/* Bits for running on 64-bit systems in 32-bit mode. */
232extern void *testppc64, *testppc64size;
233extern void *restorebridge, *restorebridgesize;
234extern void *rfid_patch, *rfi_patch1, *rfi_patch2;
235extern void *trapcode64;
236#endif
237
147struct pcpu __pcpu[MAXCPU];
148
149static struct trapframe frame0;
150
151char machine[] = "powerpc";
152SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "");
153
154static void cpu_startup(void *);

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232#ifndef __powerpc64__
233/* Bits for running on 64-bit systems in 32-bit mode. */
234extern void *testppc64, *testppc64size;
235extern void *restorebridge, *restorebridgesize;
236extern void *rfid_patch, *rfi_patch1, *rfi_patch2;
237extern void *trapcode64;
238#endif
239
238#ifdef SMP
239extern void *rstcode, *rstsize;
240extern void *rstcode, *rstsize;
240#endif
241extern void *trapcode, *trapsize;
242extern void *slbtrap, *slbtrapsize;
243extern void *alitrap, *alisize;
244extern void *dsitrap, *dsisize;
245extern void *decrint, *decrsize;
246extern void *extint, *extsize;
247extern void *dblow, *dbsize;
248extern void *imisstrap, *imisssize;

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486 generictrap = &trapcode;
487 }
488
489 #else /* powerpc64 */
490 cpu_features |= PPC_FEATURE_64;
491 generictrap = &trapcode;
492 #endif
493
241extern void *trapcode, *trapsize;
242extern void *slbtrap, *slbtrapsize;
243extern void *alitrap, *alisize;
244extern void *dsitrap, *dsisize;
245extern void *decrint, *decrsize;
246extern void *extint, *extsize;
247extern void *dblow, *dbsize;
248extern void *imisstrap, *imisssize;

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486 generictrap = &trapcode;
487 }
488
489 #else /* powerpc64 */
490 cpu_features |= PPC_FEATURE_64;
491 generictrap = &trapcode;
492 #endif
493
494#ifdef SMP
495 bcopy(&rstcode, (void *)(EXC_RST + trap_offset), (size_t)&rstsize);
494 bcopy(&rstcode, (void *)(EXC_RST + trap_offset), (size_t)&rstsize);
496#else
497 bcopy(generictrap, (void *)EXC_RST, (size_t)&trapsize);
498#endif
499
500#ifdef KDB
501 bcopy(&dblow, (void *)(EXC_MCHK + trap_offset), (size_t)&dbsize);
502 bcopy(&dblow, (void *)(EXC_PGM + trap_offset), (size_t)&dbsize);
503 bcopy(&dblow, (void *)(EXC_TRC + trap_offset), (size_t)&dbsize);
504 bcopy(&dblow, (void *)(EXC_BPT + trap_offset), (size_t)&dbsize);
505#else
506 bcopy(generictrap, (void *)EXC_MCHK, (size_t)&trapsize);

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781
782vm_offset_t
783pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
784{
785
786 return (pa);
787}
788
495
496#ifdef KDB
497 bcopy(&dblow, (void *)(EXC_MCHK + trap_offset), (size_t)&dbsize);
498 bcopy(&dblow, (void *)(EXC_PGM + trap_offset), (size_t)&dbsize);
499 bcopy(&dblow, (void *)(EXC_TRC + trap_offset), (size_t)&dbsize);
500 bcopy(&dblow, (void *)(EXC_BPT + trap_offset), (size_t)&dbsize);
501#else
502 bcopy(generictrap, (void *)EXC_MCHK, (size_t)&trapsize);

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777
778vm_offset_t
779pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
780{
781
782 return (pa);
783}
784
785/* From p3-53 of the MPC7450 RISC Microprocessor Family Reference Manual */
786void
787flush_disable_caches(void)
788{
789 register_t msr;
790 register_t msscr0;
791 register_t cache_reg;
792 volatile uint32_t *memp;
793 uint32_t temp;
794 int i;
795 int x;
796
797 msr = mfmsr();
798 powerpc_sync();
799 mtmsr(msr & ~(PSL_EE | PSL_DR));
800 msscr0 = mfspr(SPR_MSSCR0);
801 msscr0 &= ~MSSCR0_L2PFE;
802 mtspr(SPR_MSSCR0, msscr0);
803 powerpc_sync();
804 isync();
805 __asm__ __volatile__("dssall; sync");
806 powerpc_sync();
807 isync();
808 __asm__ __volatile__("dcbf 0,%0" :: "r"(0));
809 __asm__ __volatile__("dcbf 0,%0" :: "r"(0));
810 __asm__ __volatile__("dcbf 0,%0" :: "r"(0));
811
812 /* Lock the L1 Data cache. */
813 mtspr(SPR_LDSTCR, mfspr(SPR_LDSTCR) | 0xFF);
814 powerpc_sync();
815 isync();
816
817 mtspr(SPR_LDSTCR, 0);
818
819 /*
820 * Perform this in two stages: Flush the cache starting in RAM, then do it
821 * from ROM.
822 */
823 memp = (volatile uint32_t *)0x00000000;
824 for (i = 0; i < 128 * 1024; i++) {
825 temp = *memp;
826 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp));
827 memp += 32/sizeof(*memp);
828 }
829
830 memp = (volatile uint32_t *)0xfff00000;
831 x = 0xfe;
832
833 for (; x != 0xff;) {
834 mtspr(SPR_LDSTCR, x);
835 for (i = 0; i < 128; i++) {
836 temp = *memp;
837 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp));
838 memp += 32/sizeof(*memp);
839 }
840 x = ((x << 1) | 1) & 0xff;
841 }
842 mtspr(SPR_LDSTCR, 0);
843
844 cache_reg = mfspr(SPR_L2CR);
845 if (cache_reg & L2CR_L2E) {
846 cache_reg &= ~(L2CR_L2IO_7450 | L2CR_L2DO_7450);
847 mtspr(SPR_L2CR, cache_reg);
848 powerpc_sync();
849 mtspr(SPR_L2CR, cache_reg | L2CR_L2HWF);
850 while (mfspr(SPR_L2CR) & L2CR_L2HWF)
851 ; /* Busy wait for cache to flush */
852 powerpc_sync();
853 cache_reg &= ~L2CR_L2E;
854 mtspr(SPR_L2CR, cache_reg);
855 powerpc_sync();
856 mtspr(SPR_L2CR, cache_reg | L2CR_L2I);
857 powerpc_sync();
858 while (mfspr(SPR_L2CR) & L2CR_L2I)
859 ; /* Busy wait for L2 cache invalidate */
860 powerpc_sync();
861 }
862
863 cache_reg = mfspr(SPR_L3CR);
864 if (cache_reg & L3CR_L3E) {
865 cache_reg &= ~(L3CR_L3IO | L3CR_L3DO);
866 mtspr(SPR_L3CR, cache_reg);
867 powerpc_sync();
868 mtspr(SPR_L3CR, cache_reg | L3CR_L3HWF);
869 while (mfspr(SPR_L3CR) & L3CR_L3HWF)
870 ; /* Busy wait for cache to flush */
871 powerpc_sync();
872 cache_reg &= ~L3CR_L3E;
873 mtspr(SPR_L3CR, cache_reg);
874 powerpc_sync();
875 mtspr(SPR_L3CR, cache_reg | L3CR_L3I);
876 powerpc_sync();
877 while (mfspr(SPR_L3CR) & L3CR_L3I)
878 ; /* Busy wait for L3 cache invalidate */
879 powerpc_sync();
880 }
881
882 mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_DCE);
883 powerpc_sync();
884 isync();
885
886 mtmsr(msr);
887}
888
889void
890cpu_sleep()
891{
892 static u_quad_t timebase = 0;
893 static register_t sprgs[4];
894 static register_t srrs[2];
895
896 jmp_buf resetjb;
897 struct thread *fputd;
898 struct thread *vectd;
899 register_t hid0;
900 register_t msr;
901 register_t saved_msr;
902
903 ap_pcpu = pcpup;
904
905 PCPU_SET(restore, &resetjb);
906
907 saved_msr = mfmsr();
908 fputd = PCPU_GET(fputhread);
909 vectd = PCPU_GET(vecthread);
910 if (fputd != NULL)
911 save_fpu(fputd);
912 if (vectd != NULL)
913 save_vec(vectd);
914 if (setjmp(resetjb) == 0) {
915 sprgs[0] = mfspr(SPR_SPRG0);
916 sprgs[1] = mfspr(SPR_SPRG1);
917 sprgs[2] = mfspr(SPR_SPRG2);
918 sprgs[3] = mfspr(SPR_SPRG3);
919 srrs[0] = mfspr(SPR_SRR0);
920 srrs[1] = mfspr(SPR_SRR1);
921 timebase = mftb();
922 powerpc_sync();
923 flush_disable_caches();
924 hid0 = mfspr(SPR_HID0);
925 hid0 = (hid0 & ~(HID0_DOZE | HID0_NAP)) | HID0_SLEEP;
926 powerpc_sync();
927 isync();
928 msr = mfmsr() | PSL_POW;
929 mtspr(SPR_HID0, hid0);
930 powerpc_sync();
931
932 while (1)
933 mtmsr(msr);
934 }
935 mttb(timebase);
936 PCPU_SET(curthread, curthread);
937 PCPU_SET(curpcb, curthread->td_pcb);
938 pmap_activate(curthread);
939 powerpc_sync();
940 mtspr(SPR_SPRG0, sprgs[0]);
941 mtspr(SPR_SPRG1, sprgs[1]);
942 mtspr(SPR_SPRG2, sprgs[2]);
943 mtspr(SPR_SPRG3, sprgs[3]);
944 mtspr(SPR_SRR0, srrs[0]);
945 mtspr(SPR_SRR1, srrs[1]);
946 mtmsr(saved_msr);
947 if (fputd == curthread)
948 enable_fpu(curthread);
949 if (vectd == curthread)
950 enable_vec(curthread);
951 powerpc_sync();
952}