| NOTES (134634) | NOTES (137526) |
|---|---|
| 1# 2# NOTES -- Lines that can be cut/pasted into kernel and hints configs. 3# 4# This file contains machine dependent kernel configuration notes. For 5# machine independent notes, look in /sys/conf/NOTES. 6# | 1# 2# NOTES -- Lines that can be cut/pasted into kernel and hints configs. 3# 4# This file contains machine dependent kernel configuration notes. For 5# machine independent notes, look in /sys/conf/NOTES. 6# |
| 7# $FreeBSD: head/sys/pc98/conf/NOTES 134634 2004-09-02 12:50:47Z ru $ | 7# $FreeBSD: head/sys/pc98/conf/NOTES 137526 2004-11-10 12:24:30Z nyan $ |
| 8# 9 10# 11# This directive is mandatory; it defines the architecture to be 12# configured for; in this case, the 386 family based PC-98 and 13# compatibles. 14# 15machine pc98 --- 67 unchanged lines hidden (view full) --- 83# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct 84# mapped mode. Default is 2-way set associative mode. 85# 86# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e., enables 87# reorder). This option should not be used if you use memory mapped 88# I/O device(s). 89# 90# CPU_DISABLE_CMPXCHG disables the CMPXCHG instruction on > i386 IA32 | 8# 9 10# 11# This directive is mandatory; it defines the architecture to be 12# configured for; in this case, the 386 family based PC-98 and 13# compatibles. 14# 15machine pc98 --- 67 unchanged lines hidden (view full) --- 83# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct 84# mapped mode. Default is 2-way set associative mode. 85# 86# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e., enables 87# reorder). This option should not be used if you use memory mapped 88# I/O device(s). 89# 90# CPU_DISABLE_CMPXCHG disables the CMPXCHG instruction on > i386 IA32 |
| 91# machines. VmWare seems to emulate this instruction poorly, causing 92# the guest OS to run very slowly. Enabling this with an SMP kernel 93# will cause the kernel to be unusable. | 91# machines. VmWare 3.x seems to emulate this instruction poorly, causing 92# the guest OS to run very slowly. This problem appears to be fixed in 93# VmWare 4.x, at least in version 4.5.2, so that enabling this option with 94# VmWare 4.x will result in locking operations to be 20-30 times slower. 95# Enabling this with an SMP kernel will cause the kernel to be unusable. |
| 94# 95# CPU_DISABLE_SSE explicitly prevents I686_CPU from turning on SSE. 96# 97# CPU_ENABLE_SSE enables SSE/MMX2 instructions support. This is default 98# on I686_CPU and above. 99# 100# CPU_FASTER_5X86_FPU enables faster FPU exception handler. 101# --- 730 unchanged lines hidden --- | 96# 97# CPU_DISABLE_SSE explicitly prevents I686_CPU from turning on SSE. 98# 99# CPU_ENABLE_SSE enables SSE/MMX2 instructions support. This is default 100# on I686_CPU and above. 101# 102# CPU_FASTER_5X86_FPU enables faster FPU exception handler. 103# --- 730 unchanged lines hidden --- |