1#
2# NOTES -- Lines that can be cut/pasted into kernel and hints configs.
3#
4# This file contains machine dependent kernel configuration notes. For
5# machine independent notes, look in /sys/conf/NOTES.
6#
7# $FreeBSD: head/sys/pc98/conf/NOTES 127017 2004-03-15 10:39:37Z imp $
8#
9
10#
11# This directive is mandatory; it defines the architecture to be
12# configured for; in this case, the 386 family based PC-98 and
13# compatibles.
14#
15machine pc98
16options PC98
17
18#
19# We want LINT to cover profiling as well
20profile 2
21
22
23#####################################################################
24# SMP OPTIONS:
25#
26# The apic device enables the use of the I/O APIC for interrupt delivery.
27# The apic device can be used in both UP and SMP kernels, but is required
--- 49 unchanged lines hidden (view full) ---
77#
78# CPU_CYRIX_NO_LOCK enables weak locking for the entire address space
79# of Cyrix 6x86 and 6x86MX CPUs by setting the NO_LOCK bit of CCR1.
80# Otherwise, the NO_LOCK bit of CCR1 is cleared. (NOTE 3)
81#
82# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
83# mapped mode. Default is 2-way set associative mode.
84#
85# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
86# reorder). This option should not be used if you use memory mapped
87# I/O device(s).
88#
89# CPU_DISABLE_CMPXCHG disables the CMPXCHG instruction on > i386 IA32
90# machines. VmWare seems to emulate this instruction poorly, causing
91# the guest OS to run very slowly. Enabling this with a SMP kernel
92# will cause the kernel to be unusable.
93#
94# CPU_DISABLE_SSE explicitly prevent I686_CPU from turning on SSE.
95#
96# CPU_ENABLE_SSE enables SSE/MMX2 instructions support. This is default
97# on I686_CPU and above.
98#
99# CPU_FASTER_5X86_FPU enables faster FPU exception handler.
100#
101# CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products
102# for i386 machines.
--- 716 unchanged lines hidden ---
2# NOTES -- Lines that can be cut/pasted into kernel and hints configs.
3#
4# This file contains machine dependent kernel configuration notes. For
5# machine independent notes, look in /sys/conf/NOTES.
6#
7# $FreeBSD: head/sys/pc98/conf/NOTES 127017 2004-03-15 10:39:37Z imp $
8#
9
10#
11# This directive is mandatory; it defines the architecture to be
12# configured for; in this case, the 386 family based PC-98 and
13# compatibles.
14#
15machine pc98
16options PC98
17
18#
19# We want LINT to cover profiling as well
20profile 2
21
22
23#####################################################################
24# SMP OPTIONS:
25#
26# The apic device enables the use of the I/O APIC for interrupt delivery.
27# The apic device can be used in both UP and SMP kernels, but is required
--- 49 unchanged lines hidden (view full) ---
77#
78# CPU_CYRIX_NO_LOCK enables weak locking for the entire address space
79# of Cyrix 6x86 and 6x86MX CPUs by setting the NO_LOCK bit of CCR1.
80# Otherwise, the NO_LOCK bit of CCR1 is cleared. (NOTE 3)
81#
82# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
83# mapped mode. Default is 2-way set associative mode.
84#
85# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
86# reorder). This option should not be used if you use memory mapped
87# I/O device(s).
88#
89# CPU_DISABLE_CMPXCHG disables the CMPXCHG instruction on > i386 IA32
90# machines. VmWare seems to emulate this instruction poorly, causing
91# the guest OS to run very slowly. Enabling this with a SMP kernel
92# will cause the kernel to be unusable.
93#
94# CPU_DISABLE_SSE explicitly prevent I686_CPU from turning on SSE.
95#
96# CPU_ENABLE_SSE enables SSE/MMX2 instructions support. This is default
97# on I686_CPU and above.
98#
99# CPU_FASTER_5X86_FPU enables faster FPU exception handler.
100#
101# CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products
102# for i386 machines.
--- 716 unchanged lines hidden ---