sio.c (89485) | sio.c (90011) |
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1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 16 unchanged lines hidden (view full) --- 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * | 1/*- 2 * Copyright (c) 1991 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 16 unchanged lines hidden (view full) --- 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * |
33 * $FreeBSD: head/sys/pc98/cbus/sio.c 89485 2002-01-18 03:30:22Z nyan $ | 33 * $FreeBSD: head/sys/pc98/cbus/sio.c 90011 2002-01-31 08:26:45Z nyan $ |
34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 35 * from: i386/isa sio.c,v 1.234 36 */ 37 38#include "opt_comconsole.h" 39#include "opt_compat.h" 40#include "opt_ddb.h" 41#include "opt_sio.h" --- 300 unchanged lines hidden (view full) --- 342 struct timeval dcd_timestamp; 343 struct pps_state pps; 344 345 u_long bytes_in; /* statistics */ 346 u_long bytes_out; 347 u_int delta_error_counts[CE_NTYPES]; 348 u_long error_counts[CE_NTYPES]; 349 | 34 * from: @(#)com.c 7.5 (Berkeley) 5/16/91 35 * from: i386/isa sio.c,v 1.234 36 */ 37 38#include "opt_comconsole.h" 39#include "opt_compat.h" 40#include "opt_ddb.h" 41#include "opt_sio.h" --- 300 unchanged lines hidden (view full) --- 342 struct timeval dcd_timestamp; 343 struct pps_state pps; 344 345 u_long bytes_in; /* statistics */ 346 u_long bytes_out; 347 u_int delta_error_counts[CE_NTYPES]; 348 u_long error_counts[CE_NTYPES]; 349 |
350 u_long rclk; 351 |
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350 struct resource *irqres; 351 struct resource *ioportres; 352 void *cookie; 353 dev_t devs[6]; 354 355 /* 356 * Data area for output buffers. Someday we should build the output 357 * buffer queue without copying data. --- 8 unchanged lines hidden (view full) --- 366#endif 367}; 368 369#ifdef COM_ESP 370static int espattach __P((struct com_s *com, Port_t esp_port)); 371#endif 372 373static timeout_t siobusycheck; | 352 struct resource *irqres; 353 struct resource *ioportres; 354 void *cookie; 355 dev_t devs[6]; 356 357 /* 358 * Data area for output buffers. Someday we should build the output 359 * buffer queue without copying data. --- 8 unchanged lines hidden (view full) --- 368#endif 369}; 370 371#ifdef COM_ESP 372static int espattach __P((struct com_s *com, Port_t esp_port)); 373#endif 374 375static timeout_t siobusycheck; |
376static u_int siodivisor __P((u_long rclk, speed_t speed)); |
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374static timeout_t siodtrwakeup; 375static void comhardclose __P((struct com_s *com)); 376static void sioinput __P((struct com_s *com)); 377static void siointr1 __P((struct com_s *com)); 378static void siointr __P((void *arg)); 379static int commctl __P((struct com_s *com, int bits, int how)); 380static int comparam __P((struct tty *tp, struct termios *t)); 381static void siopoll __P((void *)); --- 35 unchanged lines hidden (view full) --- 417 /* dump */ nodump, 418 /* psize */ nopsize, 419 /* flags */ D_TTY | D_KQFILTER, 420 /* kqfilter */ ttykqfilter, 421}; 422 423int comconsole = -1; 424static volatile speed_t comdefaultrate = CONSPEED; | 377static timeout_t siodtrwakeup; 378static void comhardclose __P((struct com_s *com)); 379static void sioinput __P((struct com_s *com)); 380static void siointr1 __P((struct com_s *com)); 381static void siointr __P((void *arg)); 382static int commctl __P((struct com_s *com, int bits, int how)); 383static int comparam __P((struct tty *tp, struct termios *t)); 384static void siopoll __P((void *)); --- 35 unchanged lines hidden (view full) --- 420 /* dump */ nodump, 421 /* psize */ nopsize, 422 /* flags */ D_TTY | D_KQFILTER, 423 /* kqfilter */ ttykqfilter, 424}; 425 426int comconsole = -1; 427static volatile speed_t comdefaultrate = CONSPEED; |
428static u_long comdefaultrclk = DEFAULT_RCLK; 429SYSCTL_ULONG(_machdep, OID_AUTO, conrclk, CTLFLAG_RW, &comdefaultrclk, 0, ""); |
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425#ifdef __alpha__ 426static volatile speed_t gdbdefaultrate = CONSPEED; 427#endif 428static u_int com_events; /* input chars + weighted output completions */ 429static Port_t siocniobase; 430#ifndef __alpha__ 431static int siocnunit; 432#endif --- 89 unchanged lines hidden (view full) --- 522 { 76800, 76800, }, 523 { 20800, 20800, }, 524 { 31200, 31200, }, 525 { 41600, 41600, }, 526 { 62400, 62400, }, 527 { -1, -1 } 528}; 529static struct speedtab pc98fast_speedtab[] = { | 430#ifdef __alpha__ 431static volatile speed_t gdbdefaultrate = CONSPEED; 432#endif 433static u_int com_events; /* input chars + weighted output completions */ 434static Port_t siocniobase; 435#ifndef __alpha__ 436static int siocnunit; 437#endif --- 89 unchanged lines hidden (view full) --- 527 { 76800, 76800, }, 528 { 20800, 20800, }, 529 { 31200, 31200, }, 530 { 41600, 41600, }, 531 { 62400, 62400, }, 532 { -1, -1 } 533}; 534static struct speedtab pc98fast_speedtab[] = { |
530 { 9600, 0x80 | COMBRD(9600), }, 531 { 19200, 0x80 | COMBRD(19200), }, 532 { 38400, 0x80 | COMBRD(38400), }, 533 { 57600, 0x80 | COMBRD(57600), }, 534 { 115200, 0x80 | COMBRD(115200), }, | 535 { 9600, 0x80 | (DEFAULT_RCLK / (16 * (9600))), }, 536 { 19200, 0x80 | (DEFAULT_RCLK / (16 * (19200))), }, 537 { 38400, 0x80 | (DEFAULT_RCLK / (16 * (38400))), }, 538 { 57600, 0x80 | (DEFAULT_RCLK / (16 * (57600))), }, 539 { 115200, 0x80 | (DEFAULT_RCLK / (16 * (115200))), }, |
535 { -1, -1 } 536}; 537static struct speedtab comspeedtab_pio9032b[] = { 538 { 300, 6, }, 539 { 600, 5, }, 540 { 1200, 4, }, 541 { 2400, 3, }, 542 { 4800, 2, }, --- 12 unchanged lines hidden (view full) --- 555 { 4800, 5, }, 556 { 9600, 4, }, 557 { 19200, 3, }, 558 { 38400, 2, }, 559 { 76800, 1, }, 560 { 153600, 0, }, 561 { -1, -1 } 562}; | 540 { -1, -1 } 541}; 542static struct speedtab comspeedtab_pio9032b[] = { 543 { 300, 6, }, 544 { 600, 5, }, 545 { 1200, 4, }, 546 { 2400, 3, }, 547 { 4800, 2, }, --- 12 unchanged lines hidden (view full) --- 560 { 4800, 5, }, 561 { 9600, 4, }, 562 { 19200, 3, }, 563 { 38400, 2, }, 564 { 76800, 1, }, 565 { 153600, 0, }, 566 { -1, -1 } 567}; |
563static struct speedtab comspeedtab_mc16550[] = { | 568static struct speedtab comspeedtab_ind[] = { |
564 { 300, 1536, }, 565 { 600, 768, }, 566 { 1200, 384, }, 567 { 2400, 192, }, 568 { 4800, 96, }, 569 { 9600, 48, }, 570 { 19200, 24, }, 571 { 38400, 12, }, 572 { 57600, 8, }, 573 { 115200, 4, }, 574 { 153600, 3, }, 575 { 230400, 2, }, 576 { 460800, 1, }, 577 { -1, -1 } 578}; | 569 { 300, 1536, }, 570 { 600, 768, }, 571 { 1200, 384, }, 572 { 2400, 192, }, 573 { 4800, 96, }, 574 { 9600, 48, }, 575 { 19200, 24, }, 576 { 38400, 12, }, 577 { 57600, 8, }, 578 { 115200, 4, }, 579 { 153600, 3, }, 580 { 230400, 2, }, 581 { 460800, 1, }, 582 { -1, -1 } 583}; |
579static struct speedtab comspeedtab_rsb384[] = { 580 { 300, 3840, }, 581 { 600, 1920, }, 582 { 1200, 960, }, 583 { 2400, 480, }, 584 { 4800, 240, }, 585 { 9600, 120, }, 586 { 19200, 60, }, 587 { 38400, 30, }, 588 { 57600, 20, }, 589 { 115200, 10, }, 590 { 128000, 9, }, 591 { 144000, 8, }, 592 { 192000, 6, }, 593 { 230400, 5, }, 594 { 288000, 4, }, 595 { 384000, 3, }, 596 { 576000, 2, }, 597 { 1152000, 1, }, 598 { -1, -1 } 599}; 600static struct speedtab comspeedtab_rsa[] = { 601 { 0, 0 }, 602 { 50, COMBRD_RSA(50) }, 603 { 75, COMBRD_RSA(75) }, 604 { 110, COMBRD_RSA(110) }, 605 { 134, COMBRD_RSA(134) }, 606 { 150, COMBRD_RSA(150) }, 607 { 200, COMBRD_RSA(200) }, 608 { 300, COMBRD_RSA(300) }, 609 { 600, COMBRD_RSA(600) }, 610 { 1200, COMBRD_RSA(1200) }, 611 { 1800, COMBRD_RSA(1800) }, 612 { 2400, COMBRD_RSA(2400) }, 613 { 4800, COMBRD_RSA(4800) }, 614 { 9600, COMBRD_RSA(9600) }, 615 { 19200, COMBRD_RSA(19200) }, 616 { 38400, COMBRD_RSA(38400) }, 617 { 57600, COMBRD_RSA(57600) }, 618 { 115200, COMBRD_RSA(115200) }, 619 { 230400, COMBRD_RSA(230400) }, 620 { 460800, COMBRD_RSA(460800) }, 621 { 921600, COMBRD_RSA(921600) }, 622 { -1, -1 } 623}; 624#endif /* PC98 */ | |
625 | 584 |
626static struct speedtab comspeedtab[] = { 627 { 0, 0 }, 628 { 50, COMBRD(50) }, 629 { 75, COMBRD(75) }, 630 { 110, COMBRD(110) }, 631 { 134, COMBRD(134) }, 632 { 150, COMBRD(150) }, 633 { 200, COMBRD(200) }, 634 { 300, COMBRD(300) }, 635 { 600, COMBRD(600) }, 636 { 1200, COMBRD(1200) }, 637 { 1800, COMBRD(1800) }, 638 { 2400, COMBRD(2400) }, 639 { 4800, COMBRD(4800) }, 640 { 9600, COMBRD(9600) }, 641 { 19200, COMBRD(19200) }, 642 { 28800, COMBRD(28800) }, 643 { 38400, COMBRD(38400) }, 644 { 57600, COMBRD(57600) }, 645 { 115200, COMBRD(115200) }, 646 { -1, -1 } 647}; 648 649#ifdef PC98 | |
650struct { 651 char *name; 652 short port_table[7]; 653 short irr_mask; 654 struct speedtab *speedtab; 655 short check_irq; 656} if_8251_type[] = { 657 /* COM_IF_INTERNAL */ 658 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1}, 659 -1, pc98speedtab, 1 }, 660 /* COM_IF_PC9861K_1 */ 661 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1}, 662 3, NULL, 1 }, 663 /* COM_IF_PC9861K_2 */ 664 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1}, 665 3, NULL, 1 }, 666 /* COM_IF_IND_SS_1 */ 667 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1}, | 585struct { 586 char *name; 587 short port_table[7]; 588 short irr_mask; 589 struct speedtab *speedtab; 590 short check_irq; 591} if_8251_type[] = { 592 /* COM_IF_INTERNAL */ 593 { " (internal)", {0x30, 0x32, 0x32, 0x33, 0x35, -1, -1}, 594 -1, pc98speedtab, 1 }, 595 /* COM_IF_PC9861K_1 */ 596 { " (PC9861K)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, -1, -1}, 597 3, NULL, 1 }, 598 /* COM_IF_PC9861K_2 */ 599 { " (PC9861K)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, -1, -1}, 600 3, NULL, 1 }, 601 /* COM_IF_IND_SS_1 */ 602 { " (IND-SS)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb3, -1}, |
668 3, comspeedtab_mc16550, 1 }, | 603 3, comspeedtab_ind, 1 }, |
669 /* COM_IF_IND_SS_2 */ 670 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1}, | 604 /* COM_IF_IND_SS_2 */ 605 { " (IND-SS)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xbb, -1}, |
671 3, comspeedtab_mc16550, 1 }, | 606 3, comspeedtab_ind, 1 }, |
672 /* COM_IF_PIO9032B_1 */ 673 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1}, 674 7, comspeedtab_pio9032b, 1 }, 675 /* COM_IF_PIO9032B_2 */ 676 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1}, 677 7, comspeedtab_pio9032b, 1 }, 678 /* COM_IF_B98_01_1 */ 679 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3}, --- 30 unchanged lines hidden (view full) --- 710}; 711 712struct { 713 char *name; 714 short irr_read; 715 short irr_write; 716 bus_addr_t *iat; 717 bus_size_t iatsz; | 607 /* COM_IF_PIO9032B_1 */ 608 { " (PIO9032B)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xb8, -1}, 609 7, comspeedtab_pio9032b, 1 }, 610 /* COM_IF_PIO9032B_2 */ 611 { " (PIO9032B)", {0xb9, 0xbb, 0xbb, 0xb2, 0xb2, 0xba, -1}, 612 7, comspeedtab_pio9032b, 1 }, 613 /* COM_IF_B98_01_1 */ 614 { " (B98-01)", {0xb1, 0xb3, 0xb3, 0xb0, 0xb0, 0xd1, 0xd3}, --- 30 unchanged lines hidden (view full) --- 645}; 646 647struct { 648 char *name; 649 short irr_read; 650 short irr_write; 651 bus_addr_t *iat; 652 bus_size_t iatsz; |
718 struct speedtab *speedtab; | 653 u_long rclk; |
719} if_16550a_type[] = { 720 /* COM_IF_RSA98 */ | 654} if_16550a_type[] = { 655 /* COM_IF_RSA98 */ |
721 {" (RSA-98)", -1, -1, port_table_0, IO_COMSIZE, comspeedtab}, | 656 {" (RSA-98)", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, |
722 /* COM_IF_NS16550 */ | 657 /* COM_IF_NS16550 */ |
723 {"", -1, -1, port_table_0, IO_COMSIZE, comspeedtab}, | 658 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, |
724 /* COM_IF_SECOND_CCU */ | 659 /* COM_IF_SECOND_CCU */ |
725 {"", -1, -1, port_table_0, IO_COMSIZE, comspeedtab}, | 660 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, |
726 /* COM_IF_MC16550II */ 727 {" (MC16550II)", -1, 0x1000, port_table_8, IO_COMSIZE, | 661 /* COM_IF_MC16550II */ 662 {" (MC16550II)", -1, 0x1000, port_table_8, IO_COMSIZE, |
728 comspeedtab_mc16550}, | 663 DEFAULT_RCLK * 4}, |
729 /* COM_IF_MCRS98 */ | 664 /* COM_IF_MCRS98 */ |
730 {" (MC-RS98)", -1, 0x1000, port_table_8, IO_COMSIZE, 731 comspeedtab_mc16550}, | 665 {" (MC-RS98)", -1, 0x1000, port_table_8, IO_COMSIZE, DEFAULT_RCLK * 4}, |
732 /* COM_IF_RSB3000 */ | 666 /* COM_IF_RSB3000 */ |
733 {" (RSB-3000)", 0xbf, -1, port_table_1, IO_COMSIZE, 734 comspeedtab_rsb384}, | 667 {" (RSB-3000)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, |
735 /* COM_IF_RSB384 */ | 668 /* COM_IF_RSB384 */ |
736 {" (RSB-384)", 0xbf, -1, port_table_1, IO_COMSIZE, comspeedtab_rsb384}, | 669 {" (RSB-384)", 0xbf, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 10}, |
737 /* COM_IF_MODEM_CARD */ | 670 /* COM_IF_MODEM_CARD */ |
738 {"", -1, -1, port_table_0, IO_COMSIZE, comspeedtab}, | 671 {"", -1, -1, port_table_0, IO_COMSIZE, DEFAULT_RCLK}, |
739 /* COM_IF_RSA98III */ | 672 /* COM_IF_RSA98III */ |
740 {" (RSA-98III)", -1, -1, port_table_rsa, 16, comspeedtab_rsa}, | 673 {" (RSA-98III)", -1, -1, port_table_rsa, 16, DEFAULT_RCLK * 8}, |
741 /* COM_IF_ESP98 */ | 674 /* COM_IF_ESP98 */ |
742 {" (ESP98)", -1, -1, port_table_1, IO_COMSIZE, comspeedtab_mc16550}, | 675 {" (ESP98)", -1, -1, port_table_1, IO_COMSIZE, DEFAULT_RCLK * 4}, |
743}; 744#endif /* PC98 */ 745 746#ifdef COM_ESP 747#ifdef PC98 748 749/* XXX configure this properly. */ 750/* XXX quite broken for new-bus. */ --- 117 unchanged lines hidden (view full) --- 868 free(com->ibuf, M_DEVBUF); 869 device_set_softc(dev, NULL); 870 free(com, M_DEVBUF); 871 } 872 return (0); 873} 874 875int | 676}; 677#endif /* PC98 */ 678 679#ifdef COM_ESP 680#ifdef PC98 681 682/* XXX configure this properly. */ 683/* XXX quite broken for new-bus. */ --- 117 unchanged lines hidden (view full) --- 801 free(com->ibuf, M_DEVBUF); 802 device_set_softc(dev, NULL); 803 free(com, M_DEVBUF); 804 } 805 return (0); 806} 807 808int |
876sioprobe(dev, xrid, noprobe) | 809sioprobe(dev, xrid, rclk, noprobe) |
877 device_t dev; 878 int xrid; | 810 device_t dev; 811 int xrid; |
812 u_long rclk; |
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879 int noprobe; 880{ 881#if 0 882 static bool_t already_init; 883 device_t xdev; 884#endif 885 struct com_s *com; | 813 int noprobe; 814{ 815#if 0 816 static bool_t already_init; 817 device_t xdev; 818#endif 819 struct com_s *com; |
820 u_int divisor; |
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886 bool_t failures[10]; 887 int fn; 888 device_t idev; 889 Port_t iobase; 890 intrmask_t irqmap[4]; 891 intrmask_t irqs; 892 u_char mcr_image; 893 int result; --- 46 unchanged lines hidden (view full) --- 940#endif 941 942 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO); 943 if (com == NULL) 944 return (ENOMEM); 945 device_set_softc(dev, com); 946 com->bst = rman_get_bustag(port); 947 com->bsh = rman_get_bushandle(port); | 821 bool_t failures[10]; 822 int fn; 823 device_t idev; 824 Port_t iobase; 825 intrmask_t irqmap[4]; 826 intrmask_t irqs; 827 u_char mcr_image; 828 int result; --- 46 unchanged lines hidden (view full) --- 875#endif 876 877 com = malloc(sizeof(*com), M_DEVBUF, M_NOWAIT | M_ZERO); 878 if (com == NULL) 879 return (ENOMEM); 880 device_set_softc(dev, com); 881 com->bst = rman_get_bustag(port); 882 com->bsh = rman_get_bushandle(port); |
883#ifdef PC98 884 if (!IS_8251(iod.if_type) && rclk == 0) 885 rclk = if_16550a_type[iod.if_type & 0x0f].rclk; 886#else 887 if (rclk == 0) 888 rclk = DEFAULT_RCLK; 889#endif 890 com->rclk = rclk; |
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948 949 while (sio_inited != 2) 950 if (atomic_cmpset_int(&sio_inited, 0, 1)) { 951 mtx_init(&sio_lock, sio_driver_name, (comconsole != -1) ? 952 MTX_SPIN | MTX_QUIET : MTX_SPIN); 953 atomic_store_rel_int(&sio_inited, 2); 954 } 955 --- 211 unchanged lines hidden (view full) --- 1167 * junk after a (very fast) soft reboot and (apparently) after 1168 * master reset. 1169 * XXX what about the UART bug avoided by waiting in comparam()? 1170 * We don't want to to wait long enough to drain at 2 bps. 1171 */ 1172 if (iobase == siocniobase) 1173 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 1174 else { | 891 892 while (sio_inited != 2) 893 if (atomic_cmpset_int(&sio_inited, 0, 1)) { 894 mtx_init(&sio_lock, sio_driver_name, (comconsole != -1) ? 895 MTX_SPIN | MTX_QUIET : MTX_SPIN); 896 atomic_store_rel_int(&sio_inited, 2); 897 } 898 --- 211 unchanged lines hidden (view full) --- 1110 * junk after a (very fast) soft reboot and (apparently) after 1111 * master reset. 1112 * XXX what about the UART bug avoided by waiting in comparam()? 1113 * We don't want to to wait long enough to drain at 2 bps. 1114 */ 1115 if (iobase == siocniobase) 1116 DELAY((16 + 1) * 1000000 / (comdefaultrate / 10)); 1117 else { |
1175#ifdef PC98 1176 tmp = ttspeedtab(SIO_TEST_SPEED, 1177 if_16550a_type[iod.if_type & 0x0f].speedtab); | |
1178 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); | 1118 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); |
1179 sio_setreg(com, com_dlbl, tmp & 0xff); 1180 sio_setreg(com, com_dlbh, (tmp >> 8) & 0xff); | 1119 divisor = siodivisor(rclk, SIO_TEST_SPEED); 1120 sio_setreg(com, com_dlbl, divisor & 0xff); 1121 sio_setreg(com, com_dlbh, divisor >> 8); |
1181 sio_setreg(com, com_cfcr, CFCR_8BITS); | 1122 sio_setreg(com, com_cfcr, CFCR_8BITS); |
1182#else 1183 sio_setreg(com, com_cfcr, CFCR_DLAB | CFCR_8BITS); 1184 sio_setreg(com, com_dlbl, COMBRD(SIO_TEST_SPEED) & 0xff); 1185 sio_setreg(com, com_dlbh, (u_int) COMBRD(SIO_TEST_SPEED) >> 8); 1186 sio_setreg(com, com_cfcr, CFCR_8BITS); 1187#endif | |
1188 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 1189 } 1190 1191 /* 1192 * Enable the interrupt gate and disable device interupts. This 1193 * should leave the device driving the interrupt line low and 1194 * guarantee an edge trigger if an interrupt can be generated. 1195 */ --- 255 unchanged lines hidden (view full) --- 1451 */ 1452 com->esp = TRUE; 1453 com->esp_port = esp_port; 1454 return (1); 1455} 1456#endif /* COM_ESP */ 1457 1458int | 1123 DELAY((16 + 1) * 1000000 / (SIO_TEST_SPEED / 10)); 1124 } 1125 1126 /* 1127 * Enable the interrupt gate and disable device interupts. This 1128 * should leave the device driving the interrupt line low and 1129 * guarantee an edge trigger if an interrupt can be generated. 1130 */ --- 255 unchanged lines hidden (view full) --- 1386 */ 1387 com->esp = TRUE; 1388 com->esp_port = esp_port; 1389 return (1); 1390} 1391#endif /* COM_ESP */ 1392 1393int |
1459sioattach(dev, xrid) | 1394sioattach(dev, xrid, rclk) |
1460 device_t dev; 1461 int xrid; | 1395 device_t dev; 1396 int xrid; |
1397 u_long rclk; |
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1462{ 1463 struct com_s *com; 1464#ifdef COM_ESP 1465 Port_t *espp; 1466#endif 1467 Port_t iobase; 1468 int unit; 1469 u_int flags; --- 113 unchanged lines hidden (view full) --- 1583 com->int_id_port = iobase + com_iir; 1584 com->modem_ctl_port = iobase + com_mcr; 1585 com->mcr_image = inb(com->modem_ctl_port); 1586 com->line_status_port = iobase + com_lsr; 1587 com->modem_status_port = iobase + com_msr; 1588 com->intr_ctl_port = iobase + com_ier; 1589#endif 1590 | 1398{ 1399 struct com_s *com; 1400#ifdef COM_ESP 1401 Port_t *espp; 1402#endif 1403 Port_t iobase; 1404 int unit; 1405 u_int flags; --- 113 unchanged lines hidden (view full) --- 1519 com->int_id_port = iobase + com_iir; 1520 com->modem_ctl_port = iobase + com_mcr; 1521 com->mcr_image = inb(com->modem_ctl_port); 1522 com->line_status_port = iobase + com_lsr; 1523 com->modem_status_port = iobase + com_msr; 1524 com->intr_ctl_port = iobase + com_ier; 1525#endif 1526 |
1527#ifdef PC98 1528 if (!IS_8251(if_type) && rclk == 0) 1529 rclk = if_16550a_type[if_type & 0x0f].rclk; 1530#else 1531 if (rclk == 0) 1532 rclk = DEFAULT_RCLK; 1533#endif 1534 com->rclk = rclk; 1535 |
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1591 /* 1592 * We don't use all the flags from <sys/ttydefaults.h> since they 1593 * are only relevant for logins. It's important to have echo off 1594 * initially so that the line doesn't start blathering before the 1595 * echo flag can be turned off. 1596 */ 1597 com->it_in.c_iflag = 0; 1598 com->it_in.c_oflag = 0; --- 743 unchanged lines hidden (view full) --- 2342 com->tp->t_state &= ~TS_BUSY; 2343 ttwwakeup(com->tp); 2344 com->extra_state &= ~CSE_BUSYCHECK; 2345 } else 2346 timeout(siobusycheck, com, hz / 100); 2347 splx(s); 2348} 2349 | 1536 /* 1537 * We don't use all the flags from <sys/ttydefaults.h> since they 1538 * are only relevant for logins. It's important to have echo off 1539 * initially so that the line doesn't start blathering before the 1540 * echo flag can be turned off. 1541 */ 1542 com->it_in.c_iflag = 0; 1543 com->it_in.c_oflag = 0; --- 743 unchanged lines hidden (view full) --- 2287 com->tp->t_state &= ~TS_BUSY; 2288 ttwwakeup(com->tp); 2289 com->extra_state &= ~CSE_BUSYCHECK; 2290 } else 2291 timeout(siobusycheck, com, hz / 100); 2292 splx(s); 2293} 2294 |
2295static u_int 2296siodivisor(rclk, speed) 2297 u_long rclk; 2298 speed_t speed; 2299{ 2300 long actual_speed; 2301 u_int divisor; 2302 int error; 2303 2304 if (speed == 0 || speed > (ULONG_MAX - 1) / 8) 2305 return (0); 2306 divisor = (rclk / (8UL * speed) + 1) / 2; 2307 if (divisor == 0 || divisor >= 65536) 2308 return (0); 2309 actual_speed = rclk / (16UL * divisor); 2310 2311 /* 10 times error in percent: */ 2312 error = ((actual_speed - (long)speed) * 2000 / (long)speed + 1) / 2; 2313 2314 /* 3.0% maximum error tolerance: */ 2315 if (error < -30 || error > 30) 2316 return (0); 2317 2318 return (divisor); 2319} 2320 |
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2350static void 2351siodtrwakeup(chan) 2352 void *chan; 2353{ 2354 struct com_s *com; 2355 2356 com = (struct com_s *)chan; 2357 com->state &= ~CS_DTR_OFF; --- 858 unchanged lines hidden (view full) --- 3216static int 3217comparam(tp, t) 3218 struct tty *tp; 3219 struct termios *t; 3220{ 3221 u_int cfcr; 3222 int cflag; 3223 struct com_s *com; | 2321static void 2322siodtrwakeup(chan) 2323 void *chan; 2324{ 2325 struct com_s *com; 2326 2327 com = (struct com_s *)chan; 2328 com->state &= ~CS_DTR_OFF; --- 858 unchanged lines hidden (view full) --- 3187static int 3188comparam(tp, t) 3189 struct tty *tp; 3190 struct termios *t; 3191{ 3192 u_int cfcr; 3193 int cflag; 3194 struct com_s *com; |
3224 int divisor; | 3195 u_int divisor; |
3225 u_char dlbh; 3226 u_char dlbl; 3227 int s; 3228 int unit; 3229#ifdef PC98 3230 u_char param = 0; 3231#endif 3232 | 3196 u_char dlbh; 3197 u_char dlbl; 3198 int s; 3199 int unit; 3200#ifdef PC98 3201 u_char param = 0; 3202#endif 3203 |
3233#ifdef PC98 | |
3234 unit = DEV_TO_UNIT(tp->t_dev); 3235 com = com_addr(unit); | 3204 unit = DEV_TO_UNIT(tp->t_dev); 3205 com = com_addr(unit); |
3206 if (com == NULL) 3207 return (ENODEV); |
|
3236 | 3208 |
3209#ifdef PC98 |
|
3237 cfcr = 0; | 3210 cfcr = 0; |
3211 |
|
3238 if (IS_8251(com->pc98_if_type)) { | 3212 if (IS_8251(com->pc98_if_type)) { |
3239 divisor = pc98_ttspeedtab(com, t->c_ospeed); | 3213 divisor = (int) pc98_ttspeedtab(com, t->c_ospeed); 3214 if ((int)divisor < 0) 3215 return (EINVAL); |
3240 } else { | 3216 } else { |
3241 /* do historical conversions */ 3242 if (t->c_ispeed == 0) 3243 t->c_ispeed = t->c_ospeed; 3244 3245 /* check requested parameters */ 3246 divisor = ttspeedtab(t->c_ospeed, 3247 if_16550a_type[com->pc98_if_type & 0x0f].speedtab); 3248 } 3249#else | 3217#endif |
3250 /* do historical conversions */ 3251 if (t->c_ispeed == 0) 3252 t->c_ispeed = t->c_ospeed; 3253 3254 /* check requested parameters */ | 3218 /* do historical conversions */ 3219 if (t->c_ispeed == 0) 3220 t->c_ispeed = t->c_ospeed; 3221 3222 /* check requested parameters */ |
3255 divisor = ttspeedtab(t->c_ospeed, comspeedtab); | 3223 if (t->c_ospeed == 0) 3224 divisor = 0; 3225 else { 3226 if (t->c_ispeed != t->c_ospeed) 3227 return (EINVAL); 3228 divisor = siodivisor(com->rclk, t->c_ispeed); 3229 if (divisor == 0) 3230 return (EINVAL); 3231 } 3232#ifdef PC98 3233 } |
3256#endif | 3234#endif |
3257 if (divisor < 0 || (divisor > 0 && t->c_ispeed != t->c_ospeed)) 3258 return (EINVAL); | |
3259 | 3235 |
3260 3261#ifndef PC98 | |
3262 /* parameters are OK, convert them to the com struct and the device */ | 3236 /* parameters are OK, convert them to the com struct and the device */ |
3263 unit = DEV_TO_UNIT(tp->t_dev); 3264 com = com_addr(unit); 3265 if (com == NULL) 3266 return (ENODEV); 3267#endif | |
3268 s = spltty(); 3269#ifdef PC98 3270 if (IS_8251(com->pc98_if_type)) { 3271 if (divisor == 0) 3272 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3273 else 3274 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3275 } else --- 77 unchanged lines hidden (view full) --- 3353 * Only set the divisor registers if they would change, 3354 * since on some 16550 incompatibles (UMC8669F), setting 3355 * them while input is arriving them loses sync until 3356 * data stops arriving. 3357 */ 3358 dlbl = divisor & 0xFF; 3359 if (sio_getreg(com, com_dlbl) != dlbl) 3360 sio_setreg(com, com_dlbl, dlbl); | 3237 s = spltty(); 3238#ifdef PC98 3239 if (IS_8251(com->pc98_if_type)) { 3240 if (divisor == 0) 3241 com_tiocm_bic(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3242 else 3243 com_tiocm_bis(com, TIOCM_DTR|TIOCM_RTS|TIOCM_LE); 3244 } else --- 77 unchanged lines hidden (view full) --- 3322 * Only set the divisor registers if they would change, 3323 * since on some 16550 incompatibles (UMC8669F), setting 3324 * them while input is arriving them loses sync until 3325 * data stops arriving. 3326 */ 3327 dlbl = divisor & 0xFF; 3328 if (sio_getreg(com, com_dlbl) != dlbl) 3329 sio_setreg(com, com_dlbl, dlbl); |
3361 dlbh = (u_int) divisor >> 8; | 3330 dlbh = divisor >> 8; |
3362 if (sio_getreg(com, com_dlbh) != dlbh) 3363 sio_setreg(com, com_dlbh, dlbh); 3364 } 3365 3366 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 3367#ifdef PC98 3368 } 3369#endif --- 582 unchanged lines hidden (view full) --- 3952 u_char dlbl; 3953 u_char dlbh; 3954 u_char ier; 3955 u_char cfcr; 3956 u_char mcr; 3957}; 3958 3959#ifndef __alpha__ | 3331 if (sio_getreg(com, com_dlbh) != dlbh) 3332 sio_setreg(com, com_dlbh, dlbh); 3333 } 3334 3335 sio_setreg(com, com_cfcr, com->cfcr_image = cfcr); 3336#ifdef PC98 3337 } 3338#endif --- 582 unchanged lines hidden (view full) --- 3921 u_char dlbl; 3922 u_char dlbh; 3923 u_char ier; 3924 u_char cfcr; 3925 u_char mcr; 3926}; 3927 3928#ifndef __alpha__ |
3960static speed_t siocngetspeed __P((Port_t, struct speedtab *)); | 3929static speed_t siocngetspeed __P((Port_t, u_long rclk)); |
3961#endif 3962static void siocnclose __P((struct siocnstate *sp, Port_t iobase)); 3963static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed)); 3964static void siocntxwait __P((Port_t iobase)); 3965 3966#ifdef __alpha__ 3967int siocnattach __P((int port, int speed)); 3968int siogdbattach __P((int port, int speed)); --- 42 unchanged lines hidden (view full) --- 4011 * it's currently running at. We're assuming the serial port has 4012 * been initialized and is basicly idle. This routine is only intended 4013 * to be run at system startup. 4014 * 4015 * If the value read from the serial port doesn't make sense, return 0. 4016 */ 4017 4018static speed_t | 3930#endif 3931static void siocnclose __P((struct siocnstate *sp, Port_t iobase)); 3932static void siocnopen __P((struct siocnstate *sp, Port_t iobase, int speed)); 3933static void siocntxwait __P((Port_t iobase)); 3934 3935#ifdef __alpha__ 3936int siocnattach __P((int port, int speed)); 3937int siogdbattach __P((int port, int speed)); --- 42 unchanged lines hidden (view full) --- 3980 * it's currently running at. We're assuming the serial port has 3981 * been initialized and is basicly idle. This routine is only intended 3982 * to be run at system startup. 3983 * 3984 * If the value read from the serial port doesn't make sense, return 0. 3985 */ 3986 3987static speed_t |
4019siocngetspeed(iobase, table) 4020 Port_t iobase; 4021 struct speedtab *table; | 3988siocngetspeed(iobase, rclk) 3989 Port_t iobase; 3990 u_long rclk; |
4022{ | 3991{ |
4023 int code; | 3992 u_int divisor; |
4024 u_char dlbh; 4025 u_char dlbl; 4026 u_char cfcr; 4027 4028 cfcr = inb(iobase + com_cfcr); 4029 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 4030 4031 dlbl = inb(iobase + com_dlbl); 4032 dlbh = inb(iobase + com_dlbh); 4033 4034 outb(iobase + com_cfcr, cfcr); 4035 | 3993 u_char dlbh; 3994 u_char dlbl; 3995 u_char cfcr; 3996 3997 cfcr = inb(iobase + com_cfcr); 3998 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); 3999 4000 dlbl = inb(iobase + com_dlbl); 4001 dlbh = inb(iobase + com_dlbh); 4002 4003 outb(iobase + com_cfcr, cfcr); 4004 |
4036 code = dlbh << 8 | dlbl; | 4005 divisor = dlbh << 8 | dlbl; |
4037 | 4006 |
4038 for (; table->sp_speed != -1; table++) 4039 if (table->sp_code == code) 4040 return (table->sp_speed); 4041 4042 return (0); /* didn't match anything sane */ | 4007 /* XXX there should be more sanity checking. */ 4008 if (divisor == 0) 4009 return (CONSPEED); 4010 return (rclk / (16UL * divisor)); |
4043} 4044 4045#endif 4046 4047static void 4048siocnopen(sp, iobase, speed) 4049 struct siocnstate *sp; 4050 Port_t iobase; 4051 int speed; 4052{ | 4011} 4012 4013#endif 4014 4015static void 4016siocnopen(sp, iobase, speed) 4017 struct siocnstate *sp; 4018 Port_t iobase; 4019 int speed; 4020{ |
4053 int divisor; | 4021 u_int divisor; |
4054 u_char dlbh; 4055 u_char dlbl; 4056 4057 /* 4058 * Save all the device control registers except the fifo register 4059 * and set our default ones (cs8 -parenb speed=comdefaultrate). 4060 * We can't save the fifo register since it is read-only. 4061 */ --- 5 unchanged lines hidden (view full) --- 4067 sp->dlbl = inb(iobase + com_dlbl); 4068 sp->dlbh = inb(iobase + com_dlbh); 4069 /* 4070 * Only set the divisor registers if they would change, since on 4071 * some 16550 incompatibles (Startech), setting them clears the 4072 * data input register. This also reduces the effects of the 4073 * UMC8669F bug. 4074 */ | 4022 u_char dlbh; 4023 u_char dlbl; 4024 4025 /* 4026 * Save all the device control registers except the fifo register 4027 * and set our default ones (cs8 -parenb speed=comdefaultrate). 4028 * We can't save the fifo register since it is read-only. 4029 */ --- 5 unchanged lines hidden (view full) --- 4035 sp->dlbl = inb(iobase + com_dlbl); 4036 sp->dlbh = inb(iobase + com_dlbh); 4037 /* 4038 * Only set the divisor registers if they would change, since on 4039 * some 16550 incompatibles (Startech), setting them clears the 4040 * data input register. This also reduces the effects of the 4041 * UMC8669F bug. 4042 */ |
4075 divisor = ttspeedtab(speed, comspeedtab); | 4043 divisor = siodivisor(comdefaultrclk, speed); |
4076 dlbl = divisor & 0xFF; 4077 if (sp->dlbl != dlbl) 4078 outb(iobase + com_dlbl, dlbl); | 4044 dlbl = divisor & 0xFF; 4045 if (sp->dlbl != dlbl) 4046 outb(iobase + com_dlbl, dlbl); |
4079 dlbh = (u_int) divisor >> 8; | 4047 dlbh = divisor >> 8; |
4080 if (sp->dlbh != dlbh) 4081 outb(iobase + com_dlbh, dlbh); 4082 outb(iobase + com_cfcr, CFCR_8BITS); 4083 sp->mcr = inb(iobase + com_mcr); 4084 /* 4085 * We don't want interrupts, but must be careful not to "disable" 4086 * them by clearing the MCR_IENABLE bit, since that might cause 4087 * an interrupt by floating the IRQ line. --- 26 unchanged lines hidden (view full) --- 4114#ifndef __alpha__ 4115 4116static void 4117siocnprobe(cp) 4118 struct consdev *cp; 4119{ 4120 speed_t boot_speed; 4121 u_char cfcr; | 4048 if (sp->dlbh != dlbh) 4049 outb(iobase + com_dlbh, dlbh); 4050 outb(iobase + com_cfcr, CFCR_8BITS); 4051 sp->mcr = inb(iobase + com_mcr); 4052 /* 4053 * We don't want interrupts, but must be careful not to "disable" 4054 * them by clearing the MCR_IENABLE bit, since that might cause 4055 * an interrupt by floating the IRQ line. --- 26 unchanged lines hidden (view full) --- 4082#ifndef __alpha__ 4083 4084static void 4085siocnprobe(cp) 4086 struct consdev *cp; 4087{ 4088 speed_t boot_speed; 4089 u_char cfcr; |
4090 u_int divisor; |
|
4122 int s, unit; 4123 struct siocnstate sp; 4124 4125 /* 4126 * Find our first enabled console, if any. If it is a high-level 4127 * console device, then initialize it and return successfully. 4128 * If it is a low-level console device, then initialize it and 4129 * return unsuccessfully. It must be initialized in both cases --- 21 unchanged lines hidden (view full) --- 4151 int port; 4152 Port_t iobase; 4153 4154 if (resource_int_value("sio", unit, "port", &port)) 4155 continue; 4156 iobase = port; 4157 s = spltty(); 4158 if (boothowto & RB_SERIAL) { | 4091 int s, unit; 4092 struct siocnstate sp; 4093 4094 /* 4095 * Find our first enabled console, if any. If it is a high-level 4096 * console device, then initialize it and return successfully. 4097 * If it is a low-level console device, then initialize it and 4098 * return unsuccessfully. It must be initialized in both cases --- 21 unchanged lines hidden (view full) --- 4120 int port; 4121 Port_t iobase; 4122 4123 if (resource_int_value("sio", unit, "port", &port)) 4124 continue; 4125 iobase = port; 4126 s = spltty(); 4127 if (boothowto & RB_SERIAL) { |
4159 boot_speed = siocngetspeed(iobase, comspeedtab); | 4128 boot_speed = 4129 siocngetspeed(iobase, comdefaultrclk); |
4160 if (boot_speed) 4161 comdefaultrate = boot_speed; 4162 } 4163 4164 /* 4165 * Initialize the divisor latch. We can't rely on 4166 * siocnopen() to do this the first time, since it 4167 * avoids writing to the latch if the latch appears 4168 * to have the correct value. Also, if we didn't 4169 * just read the speed from the hardware, then we 4170 * need to set the speed in hardware so that 4171 * switching it later is null. 4172 */ 4173 cfcr = inb(iobase + com_cfcr); 4174 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); | 4130 if (boot_speed) 4131 comdefaultrate = boot_speed; 4132 } 4133 4134 /* 4135 * Initialize the divisor latch. We can't rely on 4136 * siocnopen() to do this the first time, since it 4137 * avoids writing to the latch if the latch appears 4138 * to have the correct value. Also, if we didn't 4139 * just read the speed from the hardware, then we 4140 * need to set the speed in hardware so that 4141 * switching it later is null. 4142 */ 4143 cfcr = inb(iobase + com_cfcr); 4144 outb(iobase + com_cfcr, CFCR_DLAB | cfcr); |
4175 outb(iobase + com_dlbl, 4176 COMBRD(comdefaultrate) & 0xff); 4177 outb(iobase + com_dlbh, 4178 (u_int) COMBRD(comdefaultrate) >> 8); | 4145 divisor = siodivisor(comdefaultrclk, comdefaultrate); 4146 outb(iobase + com_dlbl, divisor & 0xff); 4147 outb(iobase + com_dlbh, divisor >> 8); |
4179 outb(iobase + com_cfcr, cfcr); 4180 4181 siocnopen(&sp, iobase, comdefaultrate); 4182 4183 splx(s); 4184 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 4185 cp->cn_dev = makedev(CDEV_MAJOR, unit); 4186 cp->cn_pri = COM_FORCECONSOLE(flags) --- 58 unchanged lines hidden (view full) --- 4245 4246int 4247siocnattach(port, speed) 4248 int port; 4249 int speed; 4250{ 4251 int s; 4252 u_char cfcr; | 4148 outb(iobase + com_cfcr, cfcr); 4149 4150 siocnopen(&sp, iobase, comdefaultrate); 4151 4152 splx(s); 4153 if (COM_CONSOLE(flags) && !COM_LLCONSOLE(flags)) { 4154 cp->cn_dev = makedev(CDEV_MAJOR, unit); 4155 cp->cn_pri = COM_FORCECONSOLE(flags) --- 58 unchanged lines hidden (view full) --- 4214 4215int 4216siocnattach(port, speed) 4217 int port; 4218 int speed; 4219{ 4220 int s; 4221 u_char cfcr; |
4222 u_int divisor; |
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4253 struct siocnstate sp; 4254 4255 siocniobase = port; 4256 comdefaultrate = speed; 4257 sio_consdev.cn_pri = CN_NORMAL; 4258 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0); 4259 4260 s = spltty(); --- 4 unchanged lines hidden (view full) --- 4265 * avoids writing to the latch if the latch appears 4266 * to have the correct value. Also, if we didn't 4267 * just read the speed from the hardware, then we 4268 * need to set the speed in hardware so that 4269 * switching it later is null. 4270 */ 4271 cfcr = inb(siocniobase + com_cfcr); 4272 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); | 4223 struct siocnstate sp; 4224 4225 siocniobase = port; 4226 comdefaultrate = speed; 4227 sio_consdev.cn_pri = CN_NORMAL; 4228 sio_consdev.cn_dev = makedev(CDEV_MAJOR, 0); 4229 4230 s = spltty(); --- 4 unchanged lines hidden (view full) --- 4235 * avoids writing to the latch if the latch appears 4236 * to have the correct value. Also, if we didn't 4237 * just read the speed from the hardware, then we 4238 * need to set the speed in hardware so that 4239 * switching it later is null. 4240 */ 4241 cfcr = inb(siocniobase + com_cfcr); 4242 outb(siocniobase + com_cfcr, CFCR_DLAB | cfcr); |
4273 outb(siocniobase + com_dlbl, 4274 COMBRD(comdefaultrate) & 0xff); 4275 outb(siocniobase + com_dlbh, 4276 (u_int) COMBRD(comdefaultrate) >> 8); | 4243 divisor = siodivisor(comdefaultrclk, comdefaultrate); 4244 outb(siocniobase + com_dlbl, divisor & 0xff); 4245 outb(siocniobase + com_dlbh, divisor >> 8); |
4277 outb(siocniobase + com_cfcr, cfcr); 4278 4279 siocnopen(&sp, siocniobase, comdefaultrate); 4280 splx(s); 4281 4282 cnadd(&sio_consdev); 4283 return (0); 4284} 4285 4286int 4287siogdbattach(port, speed) 4288 int port; 4289 int speed; 4290{ 4291 int s; 4292 u_char cfcr; | 4246 outb(siocniobase + com_cfcr, cfcr); 4247 4248 siocnopen(&sp, siocniobase, comdefaultrate); 4249 splx(s); 4250 4251 cnadd(&sio_consdev); 4252 return (0); 4253} 4254 4255int 4256siogdbattach(port, speed) 4257 int port; 4258 int speed; 4259{ 4260 int s; 4261 u_char cfcr; |
4262 u_int divisor; |
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4293 struct siocnstate sp; 4294 int unit = 1; /* XXX !!! */ 4295 4296 siogdbiobase = port; 4297 gdbdefaultrate = speed; 4298 4299 printf("sio%d: gdb debugging port\n", unit); 4300 siogdbunit = unit; --- 11 unchanged lines hidden (view full) --- 4312 * avoids writing to the latch if the latch appears 4313 * to have the correct value. Also, if we didn't 4314 * just read the speed from the hardware, then we 4315 * need to set the speed in hardware so that 4316 * switching it later is null. 4317 */ 4318 cfcr = inb(siogdbiobase + com_cfcr); 4319 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); | 4263 struct siocnstate sp; 4264 int unit = 1; /* XXX !!! */ 4265 4266 siogdbiobase = port; 4267 gdbdefaultrate = speed; 4268 4269 printf("sio%d: gdb debugging port\n", unit); 4270 siogdbunit = unit; --- 11 unchanged lines hidden (view full) --- 4282 * avoids writing to the latch if the latch appears 4283 * to have the correct value. Also, if we didn't 4284 * just read the speed from the hardware, then we 4285 * need to set the speed in hardware so that 4286 * switching it later is null. 4287 */ 4288 cfcr = inb(siogdbiobase + com_cfcr); 4289 outb(siogdbiobase + com_cfcr, CFCR_DLAB | cfcr); |
4320 outb(siogdbiobase + com_dlbl, 4321 COMBRD(gdbdefaultrate) & 0xff); 4322 outb(siogdbiobase + com_dlbh, 4323 (u_int) COMBRD(gdbdefaultrate) >> 8); | 4290 divisor = siodivisor(comdefaultrclk, gdbdefaultrate); 4291 outb(siogdbiobase + com_dlbl, divisor & 0xff); 4292 outb(siogdbiobase + com_dlbh, divisor >> 8); |
4324 outb(siogdbiobase + com_cfcr, cfcr); 4325 4326 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4327 splx(s); 4328 4329 return (0); 4330} 4331 --- 721 unchanged lines hidden --- | 4293 outb(siogdbiobase + com_cfcr, cfcr); 4294 4295 siocnopen(&sp, siogdbiobase, gdbdefaultrate); 4296 splx(s); 4297 4298 return (0); 4299} 4300 --- 721 unchanged lines hidden --- |