1/*-
2 * Copyright (c) 2003-2009 RMI Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * RMI_BSD
30 * $FreeBSD: head/sys/mips/rmi/rmi_mips_exts.h 212366 2010-09-09 17:45:48Z jchandra $
31 */
32#ifndef __MIPS_EXTS_H__
33#define __MIPS_EXTS_H__
34
35#define CPU_BLOCKID_IFU 0
36#define CPU_BLOCKID_ICU 1
37#define CPU_BLOCKID_IEU 2
38#define CPU_BLOCKID_LSU 3

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343
344static __inline void
345write_c0_eimr64(uint64_t val)
346{
347
348 write_c0_register64(9, 7, val);
349}
350
351static __inline__ int
352xlr_test_and_set(int *lock)
353{
354 int oldval = 0;
355
356 __asm__ __volatile__(
357 ".set push\n"
358 ".set noreorder\n"
359 "move $9, %2\n"
360 "li $8, 1\n"
361 // "swapw $8, $9\n"
362 ".word 0x71280014\n"
363 "move %1, $8\n"
364 ".set pop\n"
365 : "+m"(*lock), "=r"(oldval)
366 : "r"((unsigned long)lock)
367 : "$8", "$9"
368 );
369
370 return (oldval == 0 ? 1 /* success */ : 0 /* failure */ );
371}
372
373static __inline__ uint32_t
374xlr_mfcr(uint32_t reg)
375{
376 uint32_t val;
377
378 __asm__ __volatile__(
379 "move $8, %1\n"
380 ".word 0x71090018\n"
381 "move %0, $9\n"
382 : "=r"(val)
383 : "r"(reg):"$8", "$9");
384
385 return val;
386}
387
388static __inline__ void
389xlr_mtcr(uint32_t reg, uint32_t val)
390{
391 __asm__ __volatile__(
392 "move $8, %1\n"
393 "move $9, %0\n"
394 ".word 0x71090019\n"
395 :: "r"(val), "r"(reg)
396 : "$8", "$9");
397}
398
399#if defined(__mips_n64)
400static __inline__ uint32_t
401xlr_paddr_lw(uint64_t paddr)
402{
403
404 paddr |= 0x9800000000000000ULL;
405 return (*(uint32_t *)(uintptr_t)paddr);
406}
407
408#elif defined(__mips_n32)
409static __inline__ uint32_t
410xlr_paddr_lw(uint64_t paddr)
411{
412 uint32_t val;
413
414 paddr |= 0x9800000000000000ULL;
415 __asm__ __volatile__(
416 ".set push \n\t"
417 ".set mips64 \n\t"
418 "lw %0, 0(%1) \n\t"
419 ".set pop \n"
420 : "=r"(val)
421 : "r"(paddr));
422
423 return (val);
424}
425#else
426static __inline__ uint32_t
427xlr_paddr_lw(uint64_t paddr)
428{
429 uint32_t high, low, tmp;
430
431 high = 0x98000000 | (paddr >> 32);
432 low = paddr & 0xffffffff;
433
434 __asm__ __volatile__(
435 ".set push \n\t"
436 ".set mips64 \n\t"
437 "dsll32 %1, %1, 0 \n\t"
438 "dsll32 %2, %2, 0 \n\t" /* get rid of the */
439 "dsrl32 %2, %2, 0 \n\t" /* sign extend */
440 "or %1, %1, %2 \n\t"
441 "lw %0, 0(%1) \n\t"
442 ".set pop \n"
443 : "=r"(tmp)
444 : "r"(high), "r"(low));
445
446 return tmp;
447}
448#endif
449
450/* for cpuid to hardware thread id mapping */
451extern uint32_t xlr_hw_thread_mask;
452extern int xlr_cpuid_to_hwtid[];
453extern int xlr_hwtid_to_cpuid[];
454
455#endif