| xgmac_mdio.h (198157) | xgmac_mdio.h (198626) |
|---|---|
| 1/*- 2 * Copyright (c) 2003-2009 RMI Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 21 unchanged lines hidden (view full) --- 30/* MDIO Low level Access routines */ 31/* All Phy's accessed from GMAC0 base */ 32 33#ifndef _XGMAC_MDIO_H_ 34#define _XGMAC_MDIO_H_ 35 36static inline int 37xmdio_read(volatile unsigned int *_mmio, | 1/*- 2 * Copyright (c) 2003-2009 RMI Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 21 unchanged lines hidden (view full) --- 30/* MDIO Low level Access routines */ 31/* All Phy's accessed from GMAC0 base */ 32 33#ifndef _XGMAC_MDIO_H_ 34#define _XGMAC_MDIO_H_ 35 36static inline int 37xmdio_read(volatile unsigned int *_mmio, |
| 38 uint32_t phy_addr, uint32_t address); | 38 uint32_t phy_addr, uint32_t address); |
| 39static inline void 40xmdio_write(volatile unsigned int *_mmio, | 39static inline void 40xmdio_write(volatile unsigned int *_mmio, |
| 41 uint32_t phy_addr, uint32_t address, uint32_t data); | 41 uint32_t phy_addr, uint32_t address, uint32_t data); |
| 42static inline void 43xmdio_address(volatile unsigned int *_mmio, | 42static inline void 43xmdio_address(volatile unsigned int *_mmio, |
| 44 uint32_t phy_addr, uint32_t dev_ad, uint32_t address); | 44 uint32_t phy_addr, uint32_t dev_ad, uint32_t address); |
| 45 46static inline void 47xmdio_address(volatile unsigned int *_mmio, | 45 46static inline void 47xmdio_address(volatile unsigned int *_mmio, |
| 48 uint32_t phy_addr, uint32_t dev_ad, uint32_t address) | 48 uint32_t phy_addr, uint32_t dev_ad, uint32_t address) |
| 49{ | 49{ |
| 50 uint32_t st_field = 0x0; 51 uint32_t op_type = 0x0; /* address operation */ 52 uint32_t ta_field = 0x2; /* ta field */ | 50 uint32_t st_field = 0x0; 51 uint32_t op_type = 0x0; /* address operation */ 52 uint32_t ta_field = 0x2;/* ta field */ |
| 53 54 _mmio[0x11] = ((st_field & 0x3) << 30) | | 53 54 _mmio[0x11] = ((st_field & 0x3) << 30) | |
| 55 ((op_type & 0x3) << 28) | 56 ((phy_addr & 0x1F) << 23) | 57 ((dev_ad & 0x1F) << 18) | 58 ((ta_field & 0x3) << 16) | 59 ((address & 0xffff) << 0); | 55 ((op_type & 0x3) << 28) | 56 ((phy_addr & 0x1F) << 23) | 57 ((dev_ad & 0x1F) << 18) | 58 ((ta_field & 0x3) << 16) | 59 ((address & 0xffff) << 0); |
| 60 61 _mmio[0x10] = (0x0 << 3) | 0x5; 62 _mmio[0x10] = (0x1 << 3) | 0x5; 63 _mmio[0x10] = (0x0 << 3) | 0x5; 64 65 /* wait for dev_ad cycle to complete */ 66 while (_mmio[0x14] & 0x1) { 67 }; 68 69} 70 71/* function prototypes */ 72static inline int 73xmdio_read(volatile unsigned int *_mmio, | 60 61 _mmio[0x10] = (0x0 << 3) | 0x5; 62 _mmio[0x10] = (0x1 << 3) | 0x5; 63 _mmio[0x10] = (0x0 << 3) | 0x5; 64 65 /* wait for dev_ad cycle to complete */ 66 while (_mmio[0x14] & 0x1) { 67 }; 68 69} 70 71/* function prototypes */ 72static inline int 73xmdio_read(volatile unsigned int *_mmio, |
| 74 uint32_t phy_addr, uint32_t address) | 74 uint32_t phy_addr, uint32_t address) |
| 75{ | 75{ |
| 76 uint32_t st_field = 0x0; 77 uint32_t op_type = 0x3; /* read operation */ 78 uint32_t ta_field = 0x2; /* ta field */ 79 uint32_t data = 0; | 76 uint32_t st_field = 0x0; 77 uint32_t op_type = 0x3; /* read operation */ 78 uint32_t ta_field = 0x2;/* ta field */ 79 uint32_t data = 0; |
| 80 81 xmdio_address(_mmio, phy_addr, 5, address); 82 _mmio[0x11] = ((st_field & 0x3) << 30) | | 80 81 xmdio_address(_mmio, phy_addr, 5, address); 82 _mmio[0x11] = ((st_field & 0x3) << 30) | |
| 83 ((op_type & 0x3) << 28) | 84 ((phy_addr & 0x1F) << 23) | 85 ((5 & 0x1F) << 18) | 86 ((ta_field & 0x3) << 16) | 87 ((data & 0xffff) << 0); | 83 ((op_type & 0x3) << 28) | 84 ((phy_addr & 0x1F) << 23) | 85 ((5 & 0x1F) << 18) | 86 ((ta_field & 0x3) << 16) | 87 ((data & 0xffff) << 0); |
| 88 89 _mmio[0x10] = (0x0 << 3) | 0x5; 90 _mmio[0x10] = (0x1 << 3) | 0x5; 91 _mmio[0x10] = (0x0 << 3) | 0x5; 92 93 /* wait for write cycle to complete */ 94 while (_mmio[0x14] & 0x1) { 95 }; 96 97 data = _mmio[0x11] & 0xffff; 98 return (data); 99} 100 101static inline void 102xmdio_write(volatile unsigned int *_mmio, | 88 89 _mmio[0x10] = (0x0 << 3) | 0x5; 90 _mmio[0x10] = (0x1 << 3) | 0x5; 91 _mmio[0x10] = (0x0 << 3) | 0x5; 92 93 /* wait for write cycle to complete */ 94 while (_mmio[0x14] & 0x1) { 95 }; 96 97 data = _mmio[0x11] & 0xffff; 98 return (data); 99} 100 101static inline void 102xmdio_write(volatile unsigned int *_mmio, |
| 103 uint32_t phy_addr, uint32_t address, uint32_t data) | 103 uint32_t phy_addr, uint32_t address, uint32_t data) |
| 104{ | 104{ |
| 105 uint32_t st_field = 0x0; 106 uint32_t op_type = 0x1; /* write operation */ 107 uint32_t ta_field = 0x2; /* ta field */ | 105 uint32_t st_field = 0x0; 106 uint32_t op_type = 0x1; /* write operation */ 107 uint32_t ta_field = 0x2;/* ta field */ |
| 108 109 xmdio_address(_mmio, phy_addr, 5, address); 110 _mmio[0x11] = ((st_field & 0x3) << 30) | | 108 109 xmdio_address(_mmio, phy_addr, 5, address); 110 _mmio[0x11] = ((st_field & 0x3) << 30) | |
| 111 ((op_type & 0x3) << 28) | 112 ((phy_addr & 0x1F) << 23) | 113 ((5 & 0x1F) << 18) | 114 ((ta_field & 0x3) << 16) | 115 ((data & 0xffff) << 0); | 111 ((op_type & 0x3) << 28) | 112 ((phy_addr & 0x1F) << 23) | 113 ((5 & 0x1F) << 18) | 114 ((ta_field & 0x3) << 16) | 115 ((data & 0xffff) << 0); |
| 116 117 _mmio[0x10] = (0x0 << 3) | 0x5; 118 _mmio[0x10] = (0x1 << 3) | 0x5; 119 _mmio[0x10] = (0x0 << 3) | 0x5; 120 121 /* wait for write cycle to complete */ 122 while (_mmio[0x14] & 0x1) { 123 }; 124 125} 126 127#endif | 116 117 _mmio[0x10] = (0x0 << 3) | 0x5; 118 _mmio[0x10] = (0x1 << 3) | 0x5; 119 _mmio[0x10] = (0x0 << 3) | 0x5; 120 121 /* wait for write cycle to complete */ 122 while (_mmio[0x14] & 0x1) { 123 }; 124 125} 126 127#endif |