| xlp.h (227783) | xlp.h (233533) |
|---|---|
| 1/*- 2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3 * reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * --- 12 unchanged lines hidden (view full) --- 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * NETLOGIC_BSD | 1/*- 2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3 * reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * --- 12 unchanged lines hidden (view full) --- 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * NETLOGIC_BSD |
| 29 * $FreeBSD: head/sys/mips/nlm/xlp.h 227783 2011-11-21 08:12:36Z jchandra $ | 29 * $FreeBSD: head/sys/mips/nlm/xlp.h 233533 2012-03-27 07:39:05Z jchandra $ |
| 30 */ 31 32#ifndef __NLM_XLP_H__ 33#define __NLM_XLP_H__ 34#include <mips/nlm/hal/mips-extns.h> 35#include <mips/nlm/hal/iomap.h> 36 | 30 */ 31 32#ifndef __NLM_XLP_H__ 33#define __NLM_XLP_H__ 34#include <mips/nlm/hal/mips-extns.h> 35#include <mips/nlm/hal/iomap.h> 36 |
| 37#define PIC_UART_0_IRQ 9 38#define PIC_UART_1_IRQ 10 | 37#define PIC_UART_0_IRQ 9 38#define PIC_UART_1_IRQ 10 |
| 39 | 39 |
| 40#define PIC_PCIE_0_IRQ 11 41#define PIC_PCIE_1_IRQ 12 42#define PIC_PCIE_2_IRQ 13 43#define PIC_PCIE_3_IRQ 14 | 40#define PIC_PCIE_0_IRQ 11 41#define PIC_PCIE_1_IRQ 12 42#define PIC_PCIE_2_IRQ 13 43#define PIC_PCIE_3_IRQ 14 |
| 44 | 44 |
| 45#define PIC_EHCI_0_IRQ 39 46#define PIC_EHCI_1_IRQ 42 47#define PIC_MMC_IRQ 43 | 45#define PIC_EHCI_0_IRQ 39 46/* 41 used by IRQ_SMP */ 47#define PIC_EHCI_1_IRQ 42 48#define PIC_MMC_IRQ 43 |
| 48 | 49 |
| 50 |
|
| 49/* XLP 8xx/4xx A0, A1, A2 CPU COP0 PRIDs */ 50#define CHIP_PROCESSOR_ID_XLP_8XX 0x10 51#define CHIP_PROCESSOR_ID_XLP_3XX 0x11 | 51/* XLP 8xx/4xx A0, A1, A2 CPU COP0 PRIDs */ 52#define CHIP_PROCESSOR_ID_XLP_8XX 0x10 53#define CHIP_PROCESSOR_ID_XLP_3XX 0x11 |
| 54#define CHIP_PROCESSOR_ID_XLP_416 0x94 55#define CHIP_PROCESSOR_ID_XLP_432 0x14 |
|
| 52 53/* Revision id's */ 54#define XLP_REVISION_A0 0x00 55#define XLP_REVISION_A1 0x01 56#define XLP_REVISION_A2 0x02 57#define XLP_REVISION_B0 0x03 58 59#ifndef LOCORE --- 4 unchanged lines hidden (view full) --- 64extern int xlp_ncores; 65extern int xlp_threads_per_core; 66extern uint32_t xlp_hw_thread_mask; 67extern int xlp_cpuid_to_hwtid[]; 68extern int xlp_hwtid_to_cpuid[]; 69#ifdef SMP 70extern void xlp_enable_threads(int code); 71#endif | 56 57/* Revision id's */ 58#define XLP_REVISION_A0 0x00 59#define XLP_REVISION_A1 0x01 60#define XLP_REVISION_A2 0x02 61#define XLP_REVISION_B0 0x03 62 63#ifndef LOCORE --- 4 unchanged lines hidden (view full) --- 68extern int xlp_ncores; 69extern int xlp_threads_per_core; 70extern uint32_t xlp_hw_thread_mask; 71extern int xlp_cpuid_to_hwtid[]; 72extern int xlp_hwtid_to_cpuid[]; 73#ifdef SMP 74extern void xlp_enable_threads(int code); 75#endif |
| 72uint32_t xlp_get_cpu_frequency(int core); 73void nlm_pic_irt_init(void); | 76uint32_t xlp_get_cpu_frequency(int node, int core); 77int nlm_set_device_frequency(int node, int devtype, int frequency); 78void nlm_pic_irt_init(int node); |
| 74int xlp_irt_to_irq(int irt); 75int xlp_irq_to_irt(int irq); 76int xlp_irq_is_picintr(int irq); 77 | 79int xlp_irt_to_irq(int irt); 80int xlp_irq_to_irt(int irq); 81int xlp_irq_is_picintr(int irq); 82 |
| 83static __inline int nlm_processor_id(void) 84{ 85 return ((mips_rd_prid() >> 8) & 0xff); 86} 87 |
|
| 78static __inline int nlm_is_xlp3xx(void) 79{ | 88static __inline int nlm_is_xlp3xx(void) 89{ |
| 80 int prid = (mips_rd_prid() >> 8) & 0xff; | |
| 81 | 90 |
| 82 return (prid == CHIP_PROCESSOR_ID_XLP_3XX); | 91 return (nlm_processor_id() == CHIP_PROCESSOR_ID_XLP_3XX); |
| 83} 84 | 92} 93 |
| 94static __inline int nlm_is_xlp4xx(void) 95{ 96 int prid = nlm_processor_id(); 97 98 return (prid == CHIP_PROCESSOR_ID_XLP_432 || 99 prid == CHIP_PROCESSOR_ID_XLP_416); 100} 101 |
|
| 85static __inline int nlm_is_xlp8xx(void) 86{ | 102static __inline int nlm_is_xlp8xx(void) 103{ |
| 87 int prid = (mips_rd_prid() >> 8) & 0xff; | 104 int prid = nlm_processor_id(); |
| 88 | 105 |
| 89 return (prid == CHIP_PROCESSOR_ID_XLP_8XX); | 106 return (prid == CHIP_PROCESSOR_ID_XLP_8XX || 107 prid == CHIP_PROCESSOR_ID_XLP_432 || 108 prid == CHIP_PROCESSOR_ID_XLP_416); |
| 90} 91 | 109} 110 |
| 111static __inline int nlm_is_xlp8xx_ax(void) 112{ 113 uint32_t procid = mips_rd_prid(); 114 int prid = (procid >> 8) & 0xff; 115 int rev = procid & 0xff; 116 117 return ((prid == CHIP_PROCESSOR_ID_XLP_8XX || 118 prid == CHIP_PROCESSOR_ID_XLP_432 || 119 prid == CHIP_PROCESSOR_ID_XLP_416) && 120 (rev < XLP_REVISION_B0)); 121} 122 |
|
| 92#endif /* LOCORE */ 93#endif /* __NLM_XLP_H__ */ | 123#endif /* LOCORE */ 124#endif /* __NLM_XLP_H__ */ |