| mips-extns.h (225394) | mips-extns.h (227722) |
|---|---|
| 1/*- 2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3 * reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * --- 12 unchanged lines hidden (view full) --- 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * NETLOGIC_BSD | 1/*- 2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3 * reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * --- 12 unchanged lines hidden (view full) --- 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * NETLOGIC_BSD |
| 29 * $FreeBSD: head/sys/mips/nlm/hal/mips-extns.h 225394 2011-09-05 10:45:29Z jchandra $ | 29 * $FreeBSD: head/sys/mips/nlm/hal/mips-extns.h 227722 2011-11-19 14:06:15Z jchandra $ |
| 30 */ 31 32#ifndef __NLM_MIPS_EXTNS_H__ | 30 */ 31 32#ifndef __NLM_MIPS_EXTNS_H__ |
| 33#define __NLM_MIPS_EXTNS_H__ | 33#define __NLM_MIPS_EXTNS_H__ |
| 34 35#if !defined(LOCORE) && !defined(__ASSEMBLY__) 36static __inline__ int32_t nlm_swapw(int32_t *loc, int32_t val) 37{ 38 int32_t oldval = 0; 39 40 __asm__ __volatile__ ( 41 ".set push\n" --- 68 unchanged lines hidden (view full) --- 110 : "0"(value), "r" ((unsigned long)addr) 111 : "$8", "$9"); 112 113 return (value); 114} 115/* 116 * 32 bit read write for c0 117 */ | 34 35#if !defined(LOCORE) && !defined(__ASSEMBLY__) 36static __inline__ int32_t nlm_swapw(int32_t *loc, int32_t val) 37{ 38 int32_t oldval = 0; 39 40 __asm__ __volatile__ ( 41 ".set push\n" --- 68 unchanged lines hidden (view full) --- 110 : "0"(value), "r" ((unsigned long)addr) 111 : "$8", "$9"); 112 113 return (value); 114} 115/* 116 * 32 bit read write for c0 117 */ |
| 118#define read_c0_register32(reg, sel) \ | 118#define read_c0_register32(reg, sel) \ |
| 119({ \ 120 uint32_t __rv; \ 121 __asm__ __volatile__( \ 122 ".set push\n\t" \ 123 ".set mips32\n\t" \ 124 "mfc0 %0, $%1, %2\n\t" \ 125 ".set pop\n" \ 126 : "=r" (__rv) : "i" (reg), "i" (sel) ); \ 127 __rv; \ 128 }) 129 | 119({ \ 120 uint32_t __rv; \ 121 __asm__ __volatile__( \ 122 ".set push\n\t" \ 123 ".set mips32\n\t" \ 124 "mfc0 %0, $%1, %2\n\t" \ 125 ".set pop\n" \ 126 : "=r" (__rv) : "i" (reg), "i" (sel) ); \ 127 __rv; \ 128 }) 129 |
| 130#define write_c0_register32(reg, sel, value) \ | 130#define write_c0_register32(reg, sel, value) \ |
| 131 __asm__ __volatile__( \ 132 ".set push\n\t" \ 133 ".set mips32\n\t" \ 134 "mtc0 %0, $%1, %2\n\t" \ 135 ".set pop\n" \ 136 : : "r" (value), "i" (reg), "i" (sel) ); 137 138#if defined(__mips_n64) || defined(__mips_n32) 139/* 140 * On 64 bit compilation, the operations are simple 141 */ | 131 __asm__ __volatile__( \ 132 ".set push\n\t" \ 133 ".set mips32\n\t" \ 134 "mtc0 %0, $%1, %2\n\t" \ 135 ".set pop\n" \ 136 : : "r" (value), "i" (reg), "i" (sel) ); 137 138#if defined(__mips_n64) || defined(__mips_n32) 139/* 140 * On 64 bit compilation, the operations are simple 141 */ |
| 142#define read_c0_register64(reg, sel) \ | 142#define read_c0_register64(reg, sel) \ |
| 143({ \ 144 uint64_t __rv; \ 145 __asm__ __volatile__( \ 146 ".set push\n\t" \ 147 ".set mips64\n\t" \ 148 "dmfc0 %0, $%1, %2\n\t" \ 149 ".set pop\n" \ 150 : "=r" (__rv) : "i" (reg), "i" (sel) ); \ 151 __rv; \ 152 }) 153 | 143({ \ 144 uint64_t __rv; \ 145 __asm__ __volatile__( \ 146 ".set push\n\t" \ 147 ".set mips64\n\t" \ 148 "dmfc0 %0, $%1, %2\n\t" \ 149 ".set pop\n" \ 150 : "=r" (__rv) : "i" (reg), "i" (sel) ); \ 151 __rv; \ 152 }) 153 |
| 154#define write_c0_register64(reg, sel, value) \ | 154#define write_c0_register64(reg, sel, value) \ |
| 155 __asm__ __volatile__( \ 156 ".set push\n\t" \ 157 ".set mips64\n\t" \ 158 "dmtc0 %0, $%1, %2\n\t" \ 159 ".set pop\n" \ 160 : : "r" (value), "i" (reg), "i" (sel) ); 161#else /* ! (defined(__mips_n64) || defined(__mips_n32)) */ 162 163/* 164 * 32 bit compilation, 64 bit values has to split 165 */ | 155 __asm__ __volatile__( \ 156 ".set push\n\t" \ 157 ".set mips64\n\t" \ 158 "dmtc0 %0, $%1, %2\n\t" \ 159 ".set pop\n" \ 160 : : "r" (value), "i" (reg), "i" (sel) ); 161#else /* ! (defined(__mips_n64) || defined(__mips_n32)) */ 162 163/* 164 * 32 bit compilation, 64 bit values has to split 165 */ |
| 166#define read_c0_register64(reg, sel) \ | 166#define read_c0_register64(reg, sel) \ |
| 167({ \ 168 uint32_t __high, __low; \ 169 __asm__ __volatile__( \ 170 ".set push\n\t" \ 171 ".set noreorder\n\t" \ 172 ".set mips64\n\t" \ 173 "dmfc0 $8, $%2, %3\n\t" \ 174 "dsra32 %0, $8, 0\n\t" \ 175 "sll %1, $8, 0\n\t" \ 176 ".set pop\n" \ 177 : "=r"(__high), "=r"(__low): "i"(reg), "i"(sel) \ 178 : "$8"); \ 179 ((uint64_t)__high << 32) | __low; \ 180}) 181 | 167({ \ 168 uint32_t __high, __low; \ 169 __asm__ __volatile__( \ 170 ".set push\n\t" \ 171 ".set noreorder\n\t" \ 172 ".set mips64\n\t" \ 173 "dmfc0 $8, $%2, %3\n\t" \ 174 "dsra32 %0, $8, 0\n\t" \ 175 "sll %1, $8, 0\n\t" \ 176 ".set pop\n" \ 177 : "=r"(__high), "=r"(__low): "i"(reg), "i"(sel) \ 178 : "$8"); \ 179 ((uint64_t)__high << 32) | __low; \ 180}) 181 |
| 182#define write_c0_register64(reg, sel, value) \ | 182#define write_c0_register64(reg, sel, value) \ |
| 183do { \ 184 uint32_t __high = value >> 32; \ 185 uint32_t __low = value & 0xffffffff; \ 186 __asm__ __volatile__( \ 187 ".set push\n\t" \ 188 ".set noreorder\n\t" \ 189 ".set mips64\n\t" \ 190 "dsll32 $8, %1, 0\n\t" \ --- 71 unchanged lines hidden (view full) --- 262 263static __inline__ int 264nlm_coreid(void) 265{ 266 return (nlm_read_c0_ebase() >> 2) & 0x7; 267} 268#endif 269 | 183do { \ 184 uint32_t __high = value >> 32; \ 185 uint32_t __low = value & 0xffffffff; \ 186 __asm__ __volatile__( \ 187 ".set push\n\t" \ 188 ".set noreorder\n\t" \ 189 ".set mips64\n\t" \ 190 "dsll32 $8, %1, 0\n\t" \ --- 71 unchanged lines hidden (view full) --- 262 263static __inline__ int 264nlm_coreid(void) 265{ 266 return (nlm_read_c0_ebase() >> 2) & 0x7; 267} 268#endif 269 |
| 270#define XLP_MAX_NODES 4 271#define XLP_MAX_CORES 8 272#define XLP_MAX_THREADS 4 | 270#define XLP_MAX_NODES 4 271#define XLP_MAX_CORES 8 272#define XLP_MAX_THREADS 4 |
| 273 274#endif | 273 274#endif |