| iomap.h (225394) | iomap.h (227722) |
|---|---|
| 1/*- 2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3 * reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * --- 12 unchanged lines hidden (view full) --- 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * NETLOGIC_BSD | 1/*- 2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3 * reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * --- 12 unchanged lines hidden (view full) --- 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * NETLOGIC_BSD |
| 29 * $FreeBSD: head/sys/mips/nlm/hal/iomap.h 225394 2011-09-05 10:45:29Z jchandra $ | 29 * $FreeBSD: head/sys/mips/nlm/hal/iomap.h 227722 2011-11-19 14:06:15Z jchandra $ |
| 30 */ 31 32#ifndef __NLM_HAL_IOMAP_H__ 33#define __NLM_HAL_IOMAP_H__ 34 | 30 */ 31 32#ifndef __NLM_HAL_IOMAP_H__ 33#define __NLM_HAL_IOMAP_H__ 34 |
| 35#define XLP_DEFAULT_IO_BASE 0x18000000 36#define NMI_BASE 0xbfc00000 | 35#define XLP_DEFAULT_IO_BASE 0x18000000 36#define NMI_BASE 0xbfc00000 |
| 37#define XLP_IO_CLK 133333333 38 | 37#define XLP_IO_CLK 133333333 38 |
| 39#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */ 40#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE) 41#define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE) 42#define XLP_IO_SIZE (64 << 20) /* ECFG space size */ 43#define XLP_IO_PCI_HDRSZ 0x100 44#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8) 45#define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \ | 39#define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */ 40#define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE) 41#define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE) 42#define XLP_IO_SIZE (64 << 20) /* ECFG space size */ 43#define XLP_IO_PCI_HDRSZ 0x100 44#define XLP_IO_DEV(node, dev) ((dev) + (node) * 8) 45#define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \ |
| 46 ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12)) 47 | 46 ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12)) 47 |
| 48#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0) | 48#define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0) |
| 49/* coherent inter chip */ | 49/* coherent inter chip */ |
| 50#define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1) 51#define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2) 52#define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3) 53#define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4) | 50#define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1) 51#define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2) 52#define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3) 53#define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4) |
| 54 | 54 |
| 55#define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i) 56#define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0) 57#define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1) 58#define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2) 59#define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3) | 55#define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i) 56#define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0) 57#define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1) 58#define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2) 59#define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3) |
| 60 | 60 |
| 61#define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i) 62#define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0) 63#define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1) 64#define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2) 65#define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3) 66#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4) 67#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5) | 61#define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i) 62#define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0) 63#define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1) 64#define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2) 65#define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3) 66#define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4) 67#define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5) |
| 68 | 68 |
| 69#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0) 70#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1) | 69#define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0) 70#define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1) |
| 71 | 71 |
| 72#define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0) | 72#define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0) |
| 73 | 73 |
| 74#define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1) 75#define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2) 76#define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3) | 74#define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1) 75#define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2) 76#define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3) |
| 77 | 77 |
| 78#define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i) 79#define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0) 80#define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1) 81#define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + i) 82#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2) 83#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3) 84#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4) | 78#define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i) 79#define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0) 80#define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1) 81#define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + (i)) 82#define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2) 83#define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3) 84#define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4) |
| 85/* system management */ | 85/* system management */ |
| 86#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5) 87#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6) | 86#define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5) 87#define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6) |
| 88 | 88 |
| 89#define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0) 90#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1) 91#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2) | 89#define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0) 90#define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1) 91#define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2) |
| 92/* SD flash */ | 92/* SD flash */ |
| 93#define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3) 94#define XLP_IO_MMC_OFFSET(node, slot) \ 95 ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ) | 93#define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3) 94#define XLP_IO_MMC_OFFSET(node, slot) \ 95 ((XLP_IO_SD_OFFSET(node)) + (slot * 0x100) + XLP_IO_PCI_HDRSZ) |
| 96 97/* PCI config header register id's */ | 96 97/* PCI config header register id's */ |
| 98#define XLP_PCI_CFGREG0 0x00 99#define XLP_PCI_CFGREG1 0x01 100#define XLP_PCI_CFGREG2 0x02 101#define XLP_PCI_CFGREG3 0x03 102#define XLP_PCI_CFGREG4 0x04 103#define XLP_PCI_CFGREG5 0x05 104#define XLP_PCI_DEVINFO_REG0 0x30 105#define XLP_PCI_DEVINFO_REG1 0x31 106#define XLP_PCI_DEVINFO_REG2 0x32 107#define XLP_PCI_DEVINFO_REG3 0x33 108#define XLP_PCI_DEVINFO_REG4 0x34 109#define XLP_PCI_DEVINFO_REG5 0x35 110#define XLP_PCI_DEVINFO_REG6 0x36 111#define XLP_PCI_DEVINFO_REG7 0x37 112#define XLP_PCI_DEVSCRATCH_REG0 0x38 113#define XLP_PCI_DEVSCRATCH_REG1 0x39 114#define XLP_PCI_DEVSCRATCH_REG2 0x3a 115#define XLP_PCI_DEVSCRATCH_REG3 0x3b 116#define XLP_PCI_MSGSTN_REG 0x3c 117#define XLP_PCI_IRTINFO_REG 0x3d 118#define XLP_PCI_UCODEINFO_REG 0x3e 119#define XLP_PCI_SBB_WT_REG 0x3f | 98#define XLP_PCI_CFGREG0 0x00 99#define XLP_PCI_CFGREG1 0x01 100#define XLP_PCI_CFGREG2 0x02 101#define XLP_PCI_CFGREG3 0x03 102#define XLP_PCI_CFGREG4 0x04 103#define XLP_PCI_CFGREG5 0x05 104#define XLP_PCI_DEVINFO_REG0 0x30 105#define XLP_PCI_DEVINFO_REG1 0x31 106#define XLP_PCI_DEVINFO_REG2 0x32 107#define XLP_PCI_DEVINFO_REG3 0x33 108#define XLP_PCI_DEVINFO_REG4 0x34 109#define XLP_PCI_DEVINFO_REG5 0x35 110#define XLP_PCI_DEVINFO_REG6 0x36 111#define XLP_PCI_DEVINFO_REG7 0x37 112#define XLP_PCI_DEVSCRATCH_REG0 0x38 113#define XLP_PCI_DEVSCRATCH_REG1 0x39 114#define XLP_PCI_DEVSCRATCH_REG2 0x3a 115#define XLP_PCI_DEVSCRATCH_REG3 0x3b 116#define XLP_PCI_MSGSTN_REG 0x3c 117#define XLP_PCI_IRTINFO_REG 0x3d 118#define XLP_PCI_UCODEINFO_REG 0x3e 119#define XLP_PCI_SBB_WT_REG 0x3f |
| 120 121/* PCI IDs for SoC device */ 122#define PCI_VENDOR_NETLOGIC 0x184e 123 124#define PCI_DEVICE_ID_NLM_ROOT 0x1001 125#define PCI_DEVICE_ID_NLM_ICI 0x1002 126#define PCI_DEVICE_ID_NLM_PIC 0x1003 127#define PCI_DEVICE_ID_NLM_PCIE 0x1004 --- 9 unchanged lines hidden (view full) --- 137#define PCI_DEVICE_ID_NLM_UART 0x1010 138#define PCI_DEVICE_ID_NLM_I2C 0x1011 139#define PCI_DEVICE_ID_NLM_NOR 0x1015 140#define PCI_DEVICE_ID_NLM_NAND 0x1016 141#define PCI_DEVICE_ID_NLM_MMC 0x1018 142 143#if !defined(LOCORE) && !defined(__ASSEMBLY__) 144 | 120 121/* PCI IDs for SoC device */ 122#define PCI_VENDOR_NETLOGIC 0x184e 123 124#define PCI_DEVICE_ID_NLM_ROOT 0x1001 125#define PCI_DEVICE_ID_NLM_ICI 0x1002 126#define PCI_DEVICE_ID_NLM_PIC 0x1003 127#define PCI_DEVICE_ID_NLM_PCIE 0x1004 --- 9 unchanged lines hidden (view full) --- 137#define PCI_DEVICE_ID_NLM_UART 0x1010 138#define PCI_DEVICE_ID_NLM_I2C 0x1011 139#define PCI_DEVICE_ID_NLM_NOR 0x1015 140#define PCI_DEVICE_ID_NLM_NAND 0x1016 141#define PCI_DEVICE_ID_NLM_MMC 0x1018 142 143#if !defined(LOCORE) && !defined(__ASSEMBLY__) 144 |
| 145#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r) 146#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v) | 145#define nlm_read_pci_reg(b, r) nlm_read_reg(b, r) 146#define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v) |
| 147 148extern uint64_t xlp_sys_base; 149extern uint64_t xlp_pic_base; 150#endif /* !LOCORE or !__ASSEMBLY */ 151 152#endif /* __NLM_HAL_IOMAP_H__ */ | 147 148extern uint64_t xlp_sys_base; 149extern uint64_t xlp_pic_base; 150#endif /* !LOCORE or !__ASSEMBLY */ 151 152#endif /* __NLM_HAL_IOMAP_H__ */ |