| cpucontrol.h (225394) | cpucontrol.h (227722) |
|---|---|
| 1/*- 2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3 * reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * --- 12 unchanged lines hidden (view full) --- 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * NETLOGIC_BSD | 1/*- 2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3 * reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * --- 12 unchanged lines hidden (view full) --- 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * NETLOGIC_BSD |
| 29 * $FreeBSD: head/sys/mips/nlm/hal/cpucontrol.h 225394 2011-09-05 10:45:29Z jchandra $ | 29 * $FreeBSD: head/sys/mips/nlm/hal/cpucontrol.h 227722 2011-11-19 14:06:15Z jchandra $ |
| 30 */ 31 32#ifndef __NLM_HAL_CPUCONTROL_H__ | 30 */ 31 32#ifndef __NLM_HAL_CPUCONTROL_H__ |
| 33#define __NLM_HAL_CPUCONTROL_H__ | 33#define __NLM_HAL_CPUCONTROL_H__ |
| 34 | 34 |
| 35#define CPU_BLOCKID_IFU 0 36#define CPU_BLOCKID_ICU 1 37#define CPU_BLOCKID_IEU 2 38#define CPU_BLOCKID_LSU 3 39#define CPU_BLOCKID_MMU 4 40#define CPU_BLOCKID_PRF 5 41#define CPU_BLOCKID_SCH 7 42#define CPU_BLOCKID_SCU 8 43#define CPU_BLOCKID_FPU 9 44#define CPU_BLOCKID_MAP 10 | 35#define CPU_BLOCKID_IFU 0 36#define CPU_BLOCKID_ICU 1 37#define CPU_BLOCKID_IEU 2 38#define CPU_BLOCKID_LSU 3 39#define CPU_BLOCKID_MMU 4 40#define CPU_BLOCKID_PRF 5 41#define CPU_BLOCKID_SCH 7 42#define CPU_BLOCKID_SCU 8 43#define CPU_BLOCKID_FPU 9 44#define CPU_BLOCKID_MAP 10 |
| 45 | 45 |
| 46#define LSU_DEFEATURE 0x304 47#define LSU_CERRLOG_REGID 0x09 48#define SCHED_DEFEATURE 0x700 | 46#define LSU_DEFEATURE 0x304 47#define LSU_CERRLOG_REGID 0x09 48#define SCHED_DEFEATURE 0x700 |
| 49 50/* Offsets of interest from the 'MAP' Block */ | 49 50/* Offsets of interest from the 'MAP' Block */ |
| 51#define MAP_THREADMODE 0x00 52#define MAP_EXT_EBASE_ENABLE 0x04 53#define MAP_CCDI_CONFIG 0x08 54#define MAP_THRD0_CCDI_STATUS 0x0c 55#define MAP_THRD1_CCDI_STATUS 0x10 56#define MAP_THRD2_CCDI_STATUS 0x14 57#define MAP_THRD3_CCDI_STATUS 0x18 58#define MAP_THRD0_DEBUG_MODE 0x1c 59#define MAP_THRD1_DEBUG_MODE 0x20 60#define MAP_THRD2_DEBUG_MODE 0x24 61#define MAP_THRD3_DEBUG_MODE 0x28 62#define MAP_MISC_STATE 0x60 63#define MAP_DEBUG_READ_CTL 0x64 64#define MAP_DEBUG_READ_REG0 0x68 65#define MAP_DEBUG_READ_REG1 0x6c | 51#define MAP_THREADMODE 0x00 52#define MAP_EXT_EBASE_ENABLE 0x04 53#define MAP_CCDI_CONFIG 0x08 54#define MAP_THRD0_CCDI_STATUS 0x0c 55#define MAP_THRD1_CCDI_STATUS 0x10 56#define MAP_THRD2_CCDI_STATUS 0x14 57#define MAP_THRD3_CCDI_STATUS 0x18 58#define MAP_THRD0_DEBUG_MODE 0x1c 59#define MAP_THRD1_DEBUG_MODE 0x20 60#define MAP_THRD2_DEBUG_MODE 0x24 61#define MAP_THRD3_DEBUG_MODE 0x28 62#define MAP_MISC_STATE 0x60 63#define MAP_DEBUG_READ_CTL 0x64 64#define MAP_DEBUG_READ_REG0 0x68 65#define MAP_DEBUG_READ_REG1 0x6c |
| 66 | 66 |
| 67#define MMU_SETUP 0x400 68#define MMU_LFSRSEED 0x401 69#define MMU_HPW_NUM_PAGE_LVL 0x410 70#define MMU_PGWKR_PGDBASE 0x411 71#define MMU_PGWKR_PGDSHFT 0x412 72#define MMU_PGWKR_PGDMASK 0x413 73#define MMU_PGWKR_PUDSHFT 0x414 74#define MMU_PGWKR_PUDMASK 0x415 75#define MMU_PGWKR_PMDSHFT 0x416 76#define MMU_PGWKR_PMDMASK 0x417 77#define MMU_PGWKR_PTESHFT 0x418 78#define MMU_PGWKR_PTEMASK 0x419 | 67#define MMU_SETUP 0x400 68#define MMU_LFSRSEED 0x401 69#define MMU_HPW_NUM_PAGE_LVL 0x410 70#define MMU_PGWKR_PGDBASE 0x411 71#define MMU_PGWKR_PGDSHFT 0x412 72#define MMU_PGWKR_PGDMASK 0x413 73#define MMU_PGWKR_PUDSHFT 0x414 74#define MMU_PGWKR_PUDMASK 0x415 75#define MMU_PGWKR_PMDSHFT 0x416 76#define MMU_PGWKR_PMDMASK 0x417 77#define MMU_PGWKR_PTESHFT 0x418 78#define MMU_PGWKR_PTEMASK 0x419 |
| 79 80 81#if !defined(LOCORE) && !defined(__ASSEMBLY__) 82#if defined(__mips_n64) || defined(__mips_n32) 83static __inline uint64_t 84nlm_mfcr(uint32_t reg) 85{ 86 uint64_t res; --- 106 unchanged lines hidden --- | 79 80 81#if !defined(LOCORE) && !defined(__ASSEMBLY__) 82#if defined(__mips_n64) || defined(__mips_n32) 83static __inline uint64_t 84nlm_mfcr(uint32_t reg) 85{ 86 uint64_t res; --- 106 unchanged lines hidden --- |