| bridge.h (225394) | bridge.h (227722) |
|---|---|
| 1/*- 2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3 * reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * --- 12 unchanged lines hidden (view full) --- 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * NETLOGIC_BSD | 1/*- 2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3 * reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * --- 12 unchanged lines hidden (view full) --- 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * NETLOGIC_BSD |
| 29 * $FreeBSD: head/sys/mips/nlm/hal/bridge.h 225394 2011-09-05 10:45:29Z jchandra $ | 29 * $FreeBSD: head/sys/mips/nlm/hal/bridge.h 227722 2011-11-19 14:06:15Z jchandra $ |
| 30 */ 31 32#ifndef __NLM_HAL_BRIDGE_H__ | 30 */ 31 32#ifndef __NLM_HAL_BRIDGE_H__ |
| 33#define __NLM_HAL_BRIDGE_H__ | 33#define __NLM_HAL_BRIDGE_H__ |
| 34 35/** 36* @file_name mio.h 37* @author Netlogic Microsystems 38* @brief Basic definitions of XLP memory and io subsystem 39*/ 40 41/* 42 * BRIDGE specific registers 43 * 44 * These registers start after the PCIe header, which has 0x40 45 * standard entries 46 */ | 34 35/** 36* @file_name mio.h 37* @author Netlogic Microsystems 38* @brief Basic definitions of XLP memory and io subsystem 39*/ 40 41/* 42 * BRIDGE specific registers 43 * 44 * These registers start after the PCIe header, which has 0x40 45 * standard entries 46 */ |
| 47#define BRIDGE_MODE 0x00 48#define BRIDGE_PCI_CFG_BASE 0x01 49#define BRIDGE_PCI_CFG_LIMIT 0x02 50#define BRIDGE_PCIE_CFG_BASE 0x03 51#define BRIDGE_PCIE_CFG_LIMIT 0x04 52#define BRIDGE_BUSNUM_BAR0 0x05 53#define BRIDGE_BUSNUM_BAR1 0x06 54#define BRIDGE_BUSNUM_BAR2 0x07 55#define BRIDGE_BUSNUM_BAR3 0x08 56#define BRIDGE_BUSNUM_BAR4 0x09 57#define BRIDGE_BUSNUM_BAR5 0x0a 58#define BRIDGE_BUSNUM_BAR6 0x0b 59#define BRIDGE_FLASH_BAR0 0x0c 60#define BRIDGE_FLASH_BAR1 0x0d 61#define BRIDGE_FLASH_BAR2 0x0e 62#define BRIDGE_FLASH_BAR3 0x0f 63#define BRIDGE_FLASH_LIMIT0 0x10 64#define BRIDGE_FLASH_LIMIT1 0x11 65#define BRIDGE_FLASH_LIMIT2 0x12 66#define BRIDGE_FLASH_LIMIT3 0x13 | 47#define BRIDGE_MODE 0x00 48#define BRIDGE_PCI_CFG_BASE 0x01 49#define BRIDGE_PCI_CFG_LIMIT 0x02 50#define BRIDGE_PCIE_CFG_BASE 0x03 51#define BRIDGE_PCIE_CFG_LIMIT 0x04 52#define BRIDGE_BUSNUM_BAR0 0x05 53#define BRIDGE_BUSNUM_BAR1 0x06 54#define BRIDGE_BUSNUM_BAR2 0x07 55#define BRIDGE_BUSNUM_BAR3 0x08 56#define BRIDGE_BUSNUM_BAR4 0x09 57#define BRIDGE_BUSNUM_BAR5 0x0a 58#define BRIDGE_BUSNUM_BAR6 0x0b 59#define BRIDGE_FLASH_BAR0 0x0c 60#define BRIDGE_FLASH_BAR1 0x0d 61#define BRIDGE_FLASH_BAR2 0x0e 62#define BRIDGE_FLASH_BAR3 0x0f 63#define BRIDGE_FLASH_LIMIT0 0x10 64#define BRIDGE_FLASH_LIMIT1 0x11 65#define BRIDGE_FLASH_LIMIT2 0x12 66#define BRIDGE_FLASH_LIMIT3 0x13 |
| 67 | 67 |
| 68#define BRIDGE_DRAM_BAR(i) (0x14 + (i)) 69#define BRIDGE_DRAM_BAR0 0x14 70#define BRIDGE_DRAM_BAR1 0x15 71#define BRIDGE_DRAM_BAR2 0x16 72#define BRIDGE_DRAM_BAR3 0x17 73#define BRIDGE_DRAM_BAR4 0x18 74#define BRIDGE_DRAM_BAR5 0x19 75#define BRIDGE_DRAM_BAR6 0x1a 76#define BRIDGE_DRAM_BAR7 0x1b | 68#define BRIDGE_DRAM_BAR(i) (0x14 + (i)) 69#define BRIDGE_DRAM_BAR0 0x14 70#define BRIDGE_DRAM_BAR1 0x15 71#define BRIDGE_DRAM_BAR2 0x16 72#define BRIDGE_DRAM_BAR3 0x17 73#define BRIDGE_DRAM_BAR4 0x18 74#define BRIDGE_DRAM_BAR5 0x19 75#define BRIDGE_DRAM_BAR6 0x1a 76#define BRIDGE_DRAM_BAR7 0x1b |
| 77 | 77 |
| 78#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i)) 79#define BRIDGE_DRAM_LIMIT0 0x1c 80#define BRIDGE_DRAM_LIMIT1 0x1d 81#define BRIDGE_DRAM_LIMIT2 0x1e 82#define BRIDGE_DRAM_LIMIT3 0x1f 83#define BRIDGE_DRAM_LIMIT4 0x20 84#define BRIDGE_DRAM_LIMIT5 0x21 85#define BRIDGE_DRAM_LIMIT6 0x22 86#define BRIDGE_DRAM_LIMIT7 0x23 | 78#define BRIDGE_DRAM_LIMIT(i) (0x1c + (i)) 79#define BRIDGE_DRAM_LIMIT0 0x1c 80#define BRIDGE_DRAM_LIMIT1 0x1d 81#define BRIDGE_DRAM_LIMIT2 0x1e 82#define BRIDGE_DRAM_LIMIT3 0x1f 83#define BRIDGE_DRAM_LIMIT4 0x20 84#define BRIDGE_DRAM_LIMIT5 0x21 85#define BRIDGE_DRAM_LIMIT6 0x22 86#define BRIDGE_DRAM_LIMIT7 0x23 |
| 87 | 87 |
| 88#define BRIDGE_DRAM_NODE_TRANSLN0 0x24 89#define BRIDGE_DRAM_NODE_TRANSLN1 0x25 90#define BRIDGE_DRAM_NODE_TRANSLN2 0x26 91#define BRIDGE_DRAM_NODE_TRANSLN3 0x27 92#define BRIDGE_DRAM_NODE_TRANSLN4 0x28 93#define BRIDGE_DRAM_NODE_TRANSLN5 0x29 94#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a 95#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b 96#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c 97#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d 98#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e 99#define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f 100#define BRIDGE_DRAM_CHNL_TRANSLN4 0x30 101#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31 102#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32 103#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33 104#define BRIDGE_PCIEMEM_BASE0 0x34 105#define BRIDGE_PCIEMEM_BASE1 0x35 106#define BRIDGE_PCIEMEM_BASE2 0x36 107#define BRIDGE_PCIEMEM_BASE3 0x37 108#define BRIDGE_PCIEMEM_LIMIT0 0x38 109#define BRIDGE_PCIEMEM_LIMIT1 0x39 110#define BRIDGE_PCIEMEM_LIMIT2 0x3a 111#define BRIDGE_PCIEMEM_LIMIT3 0x3b 112#define BRIDGE_PCIEIO_BASE0 0x3c 113#define BRIDGE_PCIEIO_BASE1 0x3d 114#define BRIDGE_PCIEIO_BASE2 0x3e 115#define BRIDGE_PCIEIO_BASE3 0x3f 116#define BRIDGE_PCIEIO_LIMIT0 0x40 117#define BRIDGE_PCIEIO_LIMIT1 0x41 118#define BRIDGE_PCIEIO_LIMIT2 0x42 119#define BRIDGE_PCIEIO_LIMIT3 0x43 120#define BRIDGE_PCIEMEM_BASE4 0x44 121#define BRIDGE_PCIEMEM_BASE5 0x45 122#define BRIDGE_PCIEMEM_BASE6 0x46 123#define BRIDGE_PCIEMEM_LIMIT4 0x47 124#define BRIDGE_PCIEMEM_LIMIT5 0x48 125#define BRIDGE_PCIEMEM_LIMIT6 0x49 126#define BRIDGE_PCIEIO_BASE4 0x4a 127#define BRIDGE_PCIEIO_BASE5 0x4b 128#define BRIDGE_PCIEIO_BASE6 0x4c 129#define BRIDGE_PCIEIO_LIMIT4 0x4d 130#define BRIDGE_PCIEIO_LIMIT5 0x4e 131#define BRIDGE_PCIEIO_LIMIT6 0x4f 132#define BRIDGE_NBU_EVENT_CNT_CTL 0x50 133#define BRIDGE_EVNTCTR1_LOW 0x51 134#define BRIDGE_EVNTCTR1_HI 0x52 135#define BRIDGE_EVNT_CNT_CTL2 0x53 136#define BRIDGE_EVNTCTR2_LOW 0x54 137#define BRIDGE_EVNTCTR2_HI 0x55 138#define BRIDGE_TRACEBUF_MATCH0 0x56 139#define BRIDGE_TRACEBUF_MATCH1 0x57 140#define BRIDGE_TRACEBUF_MATCH_LOW 0x58 141#define BRIDGE_TRACEBUF_MATCH_HI 0x59 142#define BRIDGE_TRACEBUF_CTRL 0x5a 143#define BRIDGE_TRACEBUF_INIT 0x5b 144#define BRIDGE_TRACEBUF_ACCESS 0x5c 145#define BRIDGE_TRACEBUF_READ_DATA0 0x5d 146#define BRIDGE_TRACEBUF_READ_DATA1 0x5d 147#define BRIDGE_TRACEBUF_READ_DATA2 0x5f 148#define BRIDGE_TRACEBUF_READ_DATA3 0x60 149#define BRIDGE_TRACEBUF_STATUS 0x61 150#define BRIDGE_ADDRESS_ERROR0 0x62 151#define BRIDGE_ADDRESS_ERROR1 0x63 152#define BRIDGE_ADDRESS_ERROR2 0x64 153#define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65 154#define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66 155#define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67 156#define BRIDGE_LINE_FLUSH0 0x68 157#define BRIDGE_LINE_FLUSH1 0x69 158#define BRIDGE_NODE_ID 0x6a 159#define BRIDGE_ERROR_INTERRUPT_EN 0x6b 160#define BRIDGE_PCIE0_WEIGHT 0x2c0 161#define BRIDGE_PCIE1_WEIGHT 0x2c1 162#define BRIDGE_PCIE2_WEIGHT 0x2c2 163#define BRIDGE_PCIE3_WEIGHT 0x2c3 164#define BRIDGE_USB_WEIGHT 0x2c4 165#define BRIDGE_NET_WEIGHT 0x2c5 166#define BRIDGE_POE_WEIGHT 0x2c6 167#define BRIDGE_CMS_WEIGHT 0x2c7 168#define BRIDGE_DMAENG_WEIGHT 0x2c8 169#define BRIDGE_SEC_WEIGHT 0x2c9 170#define BRIDGE_COMP_WEIGHT 0x2ca 171#define BRIDGE_GIO_WEIGHT 0x2cb 172#define BRIDGE_FLASH_WEIGHT 0x2cc | 88#define BRIDGE_DRAM_NODE_TRANSLN0 0x24 89#define BRIDGE_DRAM_NODE_TRANSLN1 0x25 90#define BRIDGE_DRAM_NODE_TRANSLN2 0x26 91#define BRIDGE_DRAM_NODE_TRANSLN3 0x27 92#define BRIDGE_DRAM_NODE_TRANSLN4 0x28 93#define BRIDGE_DRAM_NODE_TRANSLN5 0x29 94#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a 95#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b 96#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c 97#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d 98#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e 99#define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f 100#define BRIDGE_DRAM_CHNL_TRANSLN4 0x30 101#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31 102#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32 103#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33 104#define BRIDGE_PCIEMEM_BASE0 0x34 105#define BRIDGE_PCIEMEM_BASE1 0x35 106#define BRIDGE_PCIEMEM_BASE2 0x36 107#define BRIDGE_PCIEMEM_BASE3 0x37 108#define BRIDGE_PCIEMEM_LIMIT0 0x38 109#define BRIDGE_PCIEMEM_LIMIT1 0x39 110#define BRIDGE_PCIEMEM_LIMIT2 0x3a 111#define BRIDGE_PCIEMEM_LIMIT3 0x3b 112#define BRIDGE_PCIEIO_BASE0 0x3c 113#define BRIDGE_PCIEIO_BASE1 0x3d 114#define BRIDGE_PCIEIO_BASE2 0x3e 115#define BRIDGE_PCIEIO_BASE3 0x3f 116#define BRIDGE_PCIEIO_LIMIT0 0x40 117#define BRIDGE_PCIEIO_LIMIT1 0x41 118#define BRIDGE_PCIEIO_LIMIT2 0x42 119#define BRIDGE_PCIEIO_LIMIT3 0x43 120#define BRIDGE_PCIEMEM_BASE4 0x44 121#define BRIDGE_PCIEMEM_BASE5 0x45 122#define BRIDGE_PCIEMEM_BASE6 0x46 123#define BRIDGE_PCIEMEM_LIMIT4 0x47 124#define BRIDGE_PCIEMEM_LIMIT5 0x48 125#define BRIDGE_PCIEMEM_LIMIT6 0x49 126#define BRIDGE_PCIEIO_BASE4 0x4a 127#define BRIDGE_PCIEIO_BASE5 0x4b 128#define BRIDGE_PCIEIO_BASE6 0x4c 129#define BRIDGE_PCIEIO_LIMIT4 0x4d 130#define BRIDGE_PCIEIO_LIMIT5 0x4e 131#define BRIDGE_PCIEIO_LIMIT6 0x4f 132#define BRIDGE_NBU_EVENT_CNT_CTL 0x50 133#define BRIDGE_EVNTCTR1_LOW 0x51 134#define BRIDGE_EVNTCTR1_HI 0x52 135#define BRIDGE_EVNT_CNT_CTL2 0x53 136#define BRIDGE_EVNTCTR2_LOW 0x54 137#define BRIDGE_EVNTCTR2_HI 0x55 138#define BRIDGE_TRACEBUF_MATCH0 0x56 139#define BRIDGE_TRACEBUF_MATCH1 0x57 140#define BRIDGE_TRACEBUF_MATCH_LOW 0x58 141#define BRIDGE_TRACEBUF_MATCH_HI 0x59 142#define BRIDGE_TRACEBUF_CTRL 0x5a 143#define BRIDGE_TRACEBUF_INIT 0x5b 144#define BRIDGE_TRACEBUF_ACCESS 0x5c 145#define BRIDGE_TRACEBUF_READ_DATA0 0x5d 146#define BRIDGE_TRACEBUF_READ_DATA1 0x5d 147#define BRIDGE_TRACEBUF_READ_DATA2 0x5f 148#define BRIDGE_TRACEBUF_READ_DATA3 0x60 149#define BRIDGE_TRACEBUF_STATUS 0x61 150#define BRIDGE_ADDRESS_ERROR0 0x62 151#define BRIDGE_ADDRESS_ERROR1 0x63 152#define BRIDGE_ADDRESS_ERROR2 0x64 153#define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65 154#define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66 155#define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67 156#define BRIDGE_LINE_FLUSH0 0x68 157#define BRIDGE_LINE_FLUSH1 0x69 158#define BRIDGE_NODE_ID 0x6a 159#define BRIDGE_ERROR_INTERRUPT_EN 0x6b 160#define BRIDGE_PCIE0_WEIGHT 0x2c0 161#define BRIDGE_PCIE1_WEIGHT 0x2c1 162#define BRIDGE_PCIE2_WEIGHT 0x2c2 163#define BRIDGE_PCIE3_WEIGHT 0x2c3 164#define BRIDGE_USB_WEIGHT 0x2c4 165#define BRIDGE_NET_WEIGHT 0x2c5 166#define BRIDGE_POE_WEIGHT 0x2c6 167#define BRIDGE_CMS_WEIGHT 0x2c7 168#define BRIDGE_DMAENG_WEIGHT 0x2c8 169#define BRIDGE_SEC_WEIGHT 0x2c9 170#define BRIDGE_COMP_WEIGHT 0x2ca 171#define BRIDGE_GIO_WEIGHT 0x2cb 172#define BRIDGE_FLASH_WEIGHT 0x2cc |
| 173 174#if !defined(LOCORE) && !defined(__ASSEMBLY__) 175 | 173 174#if !defined(LOCORE) && !defined(__ASSEMBLY__) 175 |
| 176#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r) 177#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v) | 176#define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r) 177#define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v) |
| 178#define nlm_get_bridge_pcibase(node) \ | 178#define nlm_get_bridge_pcibase(node) \ |
| 179 nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node)) | 179 nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node)) |
| 180#define nlm_get_bridge_regbase(node) \ | 180#define nlm_get_bridge_regbase(node) \ |
| 181 (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ) | 181 (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ) |
| 182 183#endif 184#endif | 182 183#endif 184#endif |