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1/* $OpenBSD: locore.S,v 1.18 1998/09/15 10:58:53 pefo Exp $ */
2/*-
3 * Copyright (c) 1992, 1993
4 * The Regents of the University of California. All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * Digital Equipment Corporation and Ralph Campbell.
8 *

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42 * v 1.1 89/07/11 17:55:04 nelson Exp SPRITE (DECWRL)
43 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s,
44 * v 9.2 90/01/29 18:00:39 shirriff Exp SPRITE (DECWRL)
45 * from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s,
46 * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL)
47 *
48 * from: @(#)locore.s 8.5 (Berkeley) 1/4/94
49 * JNPR: support.S,v 1.5.2.2 2007/08/29 10:03:49 girish
1/* $OpenBSD: locore.S,v 1.18 1998/09/15 10:58:53 pefo Exp $ */
2/*-
3 * Copyright (c) 1992, 1993
4 * The Regents of the University of California. All rights reserved.
5 *
6 * This code is derived from software contributed to Berkeley by
7 * Digital Equipment Corporation and Ralph Campbell.
8 *

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42 * v 1.1 89/07/11 17:55:04 nelson Exp SPRITE (DECWRL)
43 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s,
44 * v 9.2 90/01/29 18:00:39 shirriff Exp SPRITE (DECWRL)
45 * from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s,
46 * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL)
47 *
48 * from: @(#)locore.s 8.5 (Berkeley) 1/4/94
49 * JNPR: support.S,v 1.5.2.2 2007/08/29 10:03:49 girish
50 * $FreeBSD: head/sys/mips/mips/support.S 206749 2010-04-17 09:42:07Z jmallett $
50 * $FreeBSD: head/sys/mips/mips/support.S 210038 2010-07-14 00:41:22Z imp $
51 */
52
53/*
54 * Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
55 * All rights reserved.
56 *
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions

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1246 */
1247
1248 .set noreorder # Noreorder is default style!
1249
1250#if !defined(__mips_n64) && !defined(__mips_n32)
1251 /*
1252 * I don't know if these routines have the right number of
1253 * NOPs in it for all processors. XXX
51 */
52
53/*
54 * Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
55 * All rights reserved.
56 *
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions

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1246 */
1247
1248 .set noreorder # Noreorder is default style!
1249
1250#if !defined(__mips_n64) && !defined(__mips_n32)
1251 /*
1252 * I don't know if these routines have the right number of
1253 * NOPs in it for all processors. XXX
1254 *
1255 * Maybe it would be better to just leave this undefined in that case.
1254 */
1255LEAF(atomic_store_64)
1256 */
1257LEAF(atomic_store_64)
1256 mfc0 t1, COP_0_STATUS_REG
1257 and t2, t1, ~SR_INT_ENAB
1258 mtc0 t2, COP_0_STATUS_REG
1258 mfc0 t1, MIPS_COP_0_STATUS
1259 and t2, t1, ~MIPS_SR_INT_IE
1260 mtc0 t2, MIPS_COP_0_STATUS
1259 nop
1260 nop
1261 nop
1262 nop
1263 ld t0, (a1)
1264 nop
1265 nop
1266 sd t0, (a0)
1267 nop
1268 nop
1261 nop
1262 nop
1263 nop
1264 nop
1265 ld t0, (a1)
1266 nop
1267 nop
1268 sd t0, (a0)
1269 nop
1270 nop
1269 mtc0 t1,COP_0_STATUS_REG
1271 mtc0 t1,MIPS_COP_0_STATUS
1270 nop
1271 nop
1272 nop
1273 nop
1274 j ra
1275 nop
1276END(atomic_store_64)
1277
1278LEAF(atomic_load_64)
1272 nop
1273 nop
1274 nop
1275 nop
1276 j ra
1277 nop
1278END(atomic_store_64)
1279
1280LEAF(atomic_load_64)
1279 mfc0 t1, COP_0_STATUS_REG
1280 and t2, t1, ~SR_INT_ENAB
1281 mtc0 t2, COP_0_STATUS_REG
1281 mfc0 t1, MIPS_COP_0_STATUS
1282 and t2, t1, ~MIPS_SR_INT_IE
1283 mtc0 t2, MIPS_COP_0_STATUS
1282 nop
1283 nop
1284 nop
1285 nop
1286 ld t0, (a0)
1287 nop
1288 nop
1289 sd t0, (a1)
1290 nop
1291 nop
1284 nop
1285 nop
1286 nop
1287 nop
1288 ld t0, (a0)
1289 nop
1290 nop
1291 sd t0, (a1)
1292 nop
1293 nop
1292 mtc0 t1,COP_0_STATUS_REG
1294 mtc0 t1,MIPS_COP_0_STATUS
1293 nop
1294 nop
1295 nop
1296 nop
1297 j ra
1298 nop
1299END(atomic_load_64)
1300#endif

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1350
1351#endif /* DDB */
1352#endif /* DDB || DEBUG */
1353
1354#define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
1355
1356 .text
1357LEAF(breakpoint)
1295 nop
1296 nop
1297 nop
1298 nop
1299 j ra
1300 nop
1301END(atomic_load_64)
1302#endif

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1352
1353#endif /* DDB */
1354#endif /* DDB || DEBUG */
1355
1356#define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;
1357
1358 .text
1359LEAF(breakpoint)
1358 break BREAK_SOVER_VAL
1360 break MIPS_BREAK_SOVER_VAL
1359 jr ra
1360 nop
1361 END(breakpoint)
1362
1363LEAF(setjmp)
1361 jr ra
1362 nop
1363 END(breakpoint)
1364
1365LEAF(setjmp)
1364 mfc0 v0, COP_0_STATUS_REG # Later the "real" spl value!
1366 mfc0 v0, MIPS_COP_0_STATUS # Later the "real" spl value!
1365 REG_S s0, (SZREG * PREG_S0)(a0)
1366 REG_S s1, (SZREG * PREG_S1)(a0)
1367 REG_S s2, (SZREG * PREG_S2)(a0)
1368 REG_S s3, (SZREG * PREG_S3)(a0)
1369 REG_S s4, (SZREG * PREG_S4)(a0)
1370 REG_S s5, (SZREG * PREG_S5)(a0)
1371 REG_S s6, (SZREG * PREG_S6)(a0)
1372 REG_S s7, (SZREG * PREG_S7)(a0)

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1386 REG_L s2, (SZREG * PREG_S2)(a0)
1387 REG_L s3, (SZREG * PREG_S3)(a0)
1388 REG_L s4, (SZREG * PREG_S4)(a0)
1389 REG_L s5, (SZREG * PREG_S5)(a0)
1390 REG_L s6, (SZREG * PREG_S6)(a0)
1391 REG_L s7, (SZREG * PREG_S7)(a0)
1392 REG_L s8, (SZREG * PREG_S8)(a0)
1393 REG_L sp, (SZREG * PREG_SP)(a0)
1367 REG_S s0, (SZREG * PREG_S0)(a0)
1368 REG_S s1, (SZREG * PREG_S1)(a0)
1369 REG_S s2, (SZREG * PREG_S2)(a0)
1370 REG_S s3, (SZREG * PREG_S3)(a0)
1371 REG_S s4, (SZREG * PREG_S4)(a0)
1372 REG_S s5, (SZREG * PREG_S5)(a0)
1373 REG_S s6, (SZREG * PREG_S6)(a0)
1374 REG_S s7, (SZREG * PREG_S7)(a0)

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1388 REG_L s2, (SZREG * PREG_S2)(a0)
1389 REG_L s3, (SZREG * PREG_S3)(a0)
1390 REG_L s4, (SZREG * PREG_S4)(a0)
1391 REG_L s5, (SZREG * PREG_S5)(a0)
1392 REG_L s6, (SZREG * PREG_S6)(a0)
1393 REG_L s7, (SZREG * PREG_S7)(a0)
1394 REG_L s8, (SZREG * PREG_S8)(a0)
1395 REG_L sp, (SZREG * PREG_SP)(a0)
1394 mtc0 v0, COP_0_STATUS_REG # Later the "real" spl value!
1396 mtc0 v0, MIPS_COP_0_STATUS # Later the "real" spl value!
1395 ITLBNOPFIX
1396 jr ra
1397 li v0, 1 # longjmp return
1398END(longjmp)
1399
1400LEAF(fusufault)
1401 GET_CPU_PCPU(t0)
1402 lw t0, PC_CURTHREAD(t0)

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1433
1434#ifdef TARGET_OCTEON
1435/*
1436 * void octeon_enable_shadow(void)
1437 * turns on access to CC and CCRes
1438 */
1439LEAF(octeon_enable_shadow)
1440 li t1, 0x0000000f
1397 ITLBNOPFIX
1398 jr ra
1399 li v0, 1 # longjmp return
1400END(longjmp)
1401
1402LEAF(fusufault)
1403 GET_CPU_PCPU(t0)
1404 lw t0, PC_CURTHREAD(t0)

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1435
1436#ifdef TARGET_OCTEON
1437/*
1438 * void octeon_enable_shadow(void)
1439 * turns on access to CC and CCRes
1440 */
1441LEAF(octeon_enable_shadow)
1442 li t1, 0x0000000f
1441 mtc0 t1, COP_0_INFO
1443 mtc0 t1, MIPS_COP_0_INFO
1442 jr ra
1443 nop
1444END(octeon_enable_shadow)
1445
1446
1447LEAF(octeon_get_shadow)
1444 jr ra
1445 nop
1446END(octeon_enable_shadow)
1447
1448
1449LEAF(octeon_get_shadow)
1448 mfc0 v0, COP_0_INFO
1450 mfc0 v0, MIPS_COP_0_INFO
1449 jr ra
1450 nop
1451END(octeon_get_shadow)
1452
1453/*
1454 * octeon_set_control(addr, uint32_t val)
1455 */
1456LEAF(octeon_set_control)

--- 102 unchanged lines hidden --- 		1451 jr ra
1452 nop
1453END(octeon_get_shadow)
1454
1455/*
1456 * octeon_set_control(addr, uint32_t val)
1457 */
1458LEAF(octeon_set_control)

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