1/* $NetBSD: gt_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $ */
2
3/*-
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38/*
39 * PCI configuration support for gt I/O Processor chip.
40 */
41
42#include <sys/cdefs.h>
| 1/* $NetBSD: gt_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $ */
2
3/*-
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38/*
39 * PCI configuration support for gt I/O Processor chip.
40 */
41
42#include <sys/cdefs.h>
|
43__FBSDID("$FreeBSD: head/sys/mips/malta/gt_pci.c 258780 2013-11-30 22:17:27Z eadler $");
| 43__FBSDID("$FreeBSD: head/sys/mips/malta/gt_pci.c 287882 2015-09-16 23:34:51Z zbb $");
|
44
45#include <sys/param.h>
46#include <sys/systm.h>
47
48#include <sys/bus.h>
49#include <sys/endian.h>
50#include <sys/interrupt.h>
51#include <sys/malloc.h>
52#include <sys/kernel.h>
53#include <sys/module.h>
54#include <sys/rman.h>
55
56#include <vm/vm.h>
57#include <vm/pmap.h>
58#include <vm/vm_extern.h>
59
60#include <machine/bus.h>
61#include <machine/cpu.h>
62#include <machine/pmap.h>
63
64#include <mips/malta/maltareg.h>
65
66#include <mips/malta/gtreg.h>
67#include <mips/malta/gtvar.h>
68
69#include <isa/isareg.h>
70#include <dev/ic/i8259.h>
71
72#include <dev/pci/pcireg.h>
73#include <dev/pci/pcivar.h>
74
75#include <dev/pci/pcib_private.h>
76#include "pcib_if.h"
77
78#include <mips/malta/gt_pci_bus_space.h>
79
80#define ICU_LEN 16 /* number of ISA IRQs */
81
82/*
83 * XXX: These defines are from NetBSD's <dev/ic/i8259reg.h>. Respective file
84 * from FreeBSD src tree <dev/ic/i8259.h> lacks some definitions.
85 */
86#define PIC_OCW1 1
87#define PIC_OCW2 0
88#define PIC_OCW3 0
89
90#define OCW2_SELECT 0
91#define OCW2_ILS(x) ((x) << 0) /* interrupt level select */
92
93#define OCW3_POLL_IRQ(x) ((x) & 0x7f)
94#define OCW3_POLL_PENDING (1U << 7)
95
96/*
97 * Galileo controller's registers are LE so convert to then
98 * to/from native byte order. We rely on boot loader or emulator
99 * to set "swap bytes" configuration correctly for us
100 */
101#define GT_PCI_DATA(v) htole32((v))
102#define GT_HOST_DATA(v) le32toh((v))
103
104struct gt_pci_softc;
105
106struct gt_pci_intr_cookie {
107 int irq;
108 struct gt_pci_softc *sc;
109};
110
111struct gt_pci_softc {
112 device_t sc_dev;
113 bus_space_tag_t sc_st;
114 bus_space_handle_t sc_ioh_icu1;
115 bus_space_handle_t sc_ioh_icu2;
116 bus_space_handle_t sc_ioh_elcr;
117
118 int sc_busno;
119 struct rman sc_mem_rman;
120 struct rman sc_io_rman;
121 struct rman sc_irq_rman;
122 unsigned long sc_mem;
123 bus_space_handle_t sc_io;
124
125 struct resource *sc_irq;
126 struct intr_event *sc_eventstab[ICU_LEN];
127 struct gt_pci_intr_cookie sc_intr_cookies[ICU_LEN];
128 uint16_t sc_imask;
129 uint16_t sc_elcr;
130
131 uint16_t sc_reserved;
132
133 void *sc_ih;
134};
135
136static void gt_pci_set_icus(struct gt_pci_softc *);
137static int gt_pci_intr(void *v);
138static int gt_pci_probe(device_t);
139static int gt_pci_attach(device_t);
140static int gt_pci_activate_resource(device_t, device_t, int, int,
141 struct resource *);
142static int gt_pci_setup_intr(device_t, device_t, struct resource *,
143 int, driver_filter_t *, driver_intr_t *, void *, void **);
144static int gt_pci_teardown_intr(device_t, device_t, struct resource *, void*);
145static int gt_pci_maxslots(device_t );
146static int gt_pci_conf_setup(struct gt_pci_softc *, int, int, int, int,
147 uint32_t *);
148static uint32_t gt_pci_read_config(device_t, u_int, u_int, u_int, u_int, int);
149static void gt_pci_write_config(device_t, u_int, u_int, u_int, u_int,
150 uint32_t, int);
151static int gt_pci_route_interrupt(device_t pcib, device_t dev, int pin);
152static struct resource * gt_pci_alloc_resource(device_t, device_t, int,
153 int *, u_long, u_long, u_long, u_int);
154
155static void
156gt_pci_mask_irq(void *source)
157{
158 struct gt_pci_intr_cookie *cookie = source;
159 struct gt_pci_softc *sc = cookie->sc;
160 int irq = cookie->irq;
161
162 sc->sc_imask |= (1 << irq);
163 sc->sc_elcr |= (1 << irq);
164
165 gt_pci_set_icus(sc);
166}
167
168static void
169gt_pci_unmask_irq(void *source)
170{
171 struct gt_pci_intr_cookie *cookie = source;
172 struct gt_pci_softc *sc = cookie->sc;
173 int irq = cookie->irq;
174
175 /* Enable it, set trigger mode. */
176 sc->sc_imask &= ~(1 << irq);
177 sc->sc_elcr &= ~(1 << irq);
178
179 gt_pci_set_icus(sc);
180}
181
182static void
183gt_pci_set_icus(struct gt_pci_softc *sc)
184{
185 /* Enable the cascade IRQ (2) if 8-15 is enabled. */
186 if ((sc->sc_imask & 0xff00) != 0xff00)
187 sc->sc_imask &= ~(1U << 2);
188 else
189 sc->sc_imask |= (1U << 2);
190
191 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW1,
192 sc->sc_imask & 0xff);
193 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, PIC_OCW1,
194 (sc->sc_imask >> 8) & 0xff);
195
196 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
197 sc->sc_elcr & 0xff);
198 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
199 (sc->sc_elcr >> 8) & 0xff);
200}
201
202static int
203gt_pci_intr(void *v)
204{
205 struct gt_pci_softc *sc = v;
206 struct intr_event *event;
207 int irq;
208
209 for (;;) {
210 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3,
211 OCW3_SEL | OCW3_P);
212 irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3);
213 if ((irq & OCW3_POLL_PENDING) == 0)
214 {
215 return FILTER_HANDLED;
216 }
217
218 irq = OCW3_POLL_IRQ(irq);
219
220 if (irq == 2) {
221 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
222 PIC_OCW3, OCW3_SEL | OCW3_P);
223 irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu2,
224 PIC_OCW3);
225 if (irq & OCW3_POLL_PENDING)
226 irq = OCW3_POLL_IRQ(irq) + 8;
227 else
228 irq = 2;
229 }
230
231 event = sc->sc_eventstab[irq];
232
233 if (!event || TAILQ_EMPTY(&event->ie_handlers))
234 continue;
235
236 /* TODO: frame instead of NULL? */
237 intr_event_handle(event, NULL);
238 /* XXX: Log stray IRQs */
239
240 /* Send a specific EOI to the 8259. */
241 if (irq > 7) {
242 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
243 PIC_OCW2, OCW2_SELECT | OCW2_EOI | OCW2_SL |
244 OCW2_ILS(irq & 7));
245 irq = 2;
246 }
247
248 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW2,
249 OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(irq));
250 }
251
252 return FILTER_HANDLED;
253}
254
255static int
256gt_pci_probe(device_t dev)
257{
258 device_set_desc(dev, "GT64120 PCI bridge");
259 return (0);
260}
261
262static int
263gt_pci_attach(device_t dev)
264{
265
266 uint32_t busno;
267 struct gt_pci_softc *sc = device_get_softc(dev);
268 int rid;
269
270 busno = 0;
271 sc->sc_dev = dev;
272 sc->sc_busno = busno;
273 sc->sc_st = mips_bus_space_generic;
274
275 /* Use KSEG1 to access IO ports for it is uncached */
276 sc->sc_io = MIPS_PHYS_TO_KSEG1(MALTA_PCI0_IO_BASE);
277 sc->sc_io_rman.rm_type = RMAN_ARRAY;
278 sc->sc_io_rman.rm_descr = "GT64120 PCI I/O Ports";
279 /*
280 * First 256 bytes are ISA's registers: e.g. i8259's
281 * So do not use them for general purpose PCI I/O window
282 */
283 if (rman_init(&sc->sc_io_rman) != 0 ||
284 rman_manage_region(&sc->sc_io_rman, 0x100, 0xffff) != 0) {
285 panic("gt_pci_attach: failed to set up I/O rman");
286 }
287
288 /* Use KSEG1 to access PCI memory for it is uncached */
289 sc->sc_mem = MIPS_PHYS_TO_KSEG1(MALTA_PCIMEM1_BASE);
290 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
291 sc->sc_mem_rman.rm_descr = "GT64120 PCI Memory";
292 if (rman_init(&sc->sc_mem_rman) != 0 ||
293 rman_manage_region(&sc->sc_mem_rman,
294 sc->sc_mem, sc->sc_mem + MALTA_PCIMEM1_SIZE) != 0) {
295 panic("gt_pci_attach: failed to set up memory rman");
296 }
297 sc->sc_irq_rman.rm_type = RMAN_ARRAY;
298 sc->sc_irq_rman.rm_descr = "GT64120 PCI IRQs";
299 if (rman_init(&sc->sc_irq_rman) != 0 ||
300 rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0)
301 panic("gt_pci_attach: failed to set up IRQ rman");
302
303 /*
304 * Map the PIC/ELCR registers.
305 */
306#if 0
307 if (bus_space_map(sc->sc_st, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0)
308 device_printf(dev, "unable to map ELCR registers\n");
309 if (bus_space_map(sc->sc_st, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)
310 device_printf(dev, "unable to map ICU1 registers\n");
311 if (bus_space_map(sc->sc_st, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)
312 device_printf(dev, "unable to map ICU2 registers\n");
313#else
314 sc->sc_ioh_elcr = sc->sc_io + 0x4d0;
315 sc->sc_ioh_icu1 = sc->sc_io + IO_ICU1;
316 sc->sc_ioh_icu2 = sc->sc_io + IO_ICU2;
317#endif
318
319
320 /* All interrupts default to "masked off". */
321 sc->sc_imask = 0xffff;
322
323 /* All interrupts default to edge-triggered. */
324 sc->sc_elcr = 0;
325
326 /*
327 * Initialize the 8259s.
328 */
329 /* reset, program device, 4 bytes */
330 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
331 ICW1_RESET | ICW1_IC4);
332 /*
333 * XXX: values from NetBSD's <dev/ic/i8259reg.h>
334 */
335 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
336 0/*XXX*/);
337 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
338 1 << 2);
339 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
340 ICW4_8086);
341
342 /* mask all interrupts */
343 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
344 sc->sc_imask & 0xff);
345
346 /* enable special mask mode */
347 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
348 OCW3_SEL | OCW3_ESMM | OCW3_SMM);
349
350 /* read IRR by default */
351 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
352 OCW3_SEL | OCW3_RR);
353
354 /* reset, program device, 4 bytes */
355 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
356 ICW1_RESET | ICW1_IC4);
357 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
358 0/*XXX*/);
359 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
360 1 << 2);
361 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
362 ICW4_8086);
363
364 /* mask all interrupts */
365 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
366 sc->sc_imask & 0xff);
367
368 /* enable special mask mode */
369 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
370 OCW3_SEL | OCW3_ESMM | OCW3_SMM);
371
372 /* read IRR by default */
373 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
374 OCW3_SEL | OCW3_RR);
375
376 /*
377 * Default all interrupts to edge-triggered.
378 */
379 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
380 sc->sc_elcr & 0xff);
381 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
382 (sc->sc_elcr >> 8) & 0xff);
383
384 /*
385 * Some ISA interrupts are reserved for devices that
386 * we know are hard-wired to certain IRQs.
387 */
388 sc->sc_reserved =
389 (1U << 0) | /* timer */
390 (1U << 1) | /* keyboard controller (keyboard) */
391 (1U << 2) | /* PIC cascade */
392 (1U << 3) | /* COM 2 */
393 (1U << 4) | /* COM 1 */
394 (1U << 6) | /* floppy */
395 (1U << 7) | /* centronics */
396 (1U << 8) | /* RTC */
397 (1U << 9) | /* I2C */
398 (1U << 12) | /* keyboard controller (mouse) */
399 (1U << 14) | /* IDE primary */
400 (1U << 15); /* IDE secondary */
401
402 /* Hook up our interrupt handler. */
403 if ((sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
404 MALTA_SOUTHBRIDGE_INTR, MALTA_SOUTHBRIDGE_INTR, 1,
405 RF_SHAREABLE | RF_ACTIVE)) == NULL) {
406 device_printf(dev, "unable to allocate IRQ resource\n");
407 return ENXIO;
408 }
409
410 if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC,
411 gt_pci_intr, NULL, sc, &sc->sc_ih))) {
412 device_printf(dev,
413 "WARNING: unable to register interrupt handler\n");
414 return ENXIO;
415 }
416
417 /* Initialize memory and i/o rmans. */
| 44
45#include <sys/param.h>
46#include <sys/systm.h>
47
48#include <sys/bus.h>
49#include <sys/endian.h>
50#include <sys/interrupt.h>
51#include <sys/malloc.h>
52#include <sys/kernel.h>
53#include <sys/module.h>
54#include <sys/rman.h>
55
56#include <vm/vm.h>
57#include <vm/pmap.h>
58#include <vm/vm_extern.h>
59
60#include <machine/bus.h>
61#include <machine/cpu.h>
62#include <machine/pmap.h>
63
64#include <mips/malta/maltareg.h>
65
66#include <mips/malta/gtreg.h>
67#include <mips/malta/gtvar.h>
68
69#include <isa/isareg.h>
70#include <dev/ic/i8259.h>
71
72#include <dev/pci/pcireg.h>
73#include <dev/pci/pcivar.h>
74
75#include <dev/pci/pcib_private.h>
76#include "pcib_if.h"
77
78#include <mips/malta/gt_pci_bus_space.h>
79
80#define ICU_LEN 16 /* number of ISA IRQs */
81
82/*
83 * XXX: These defines are from NetBSD's <dev/ic/i8259reg.h>. Respective file
84 * from FreeBSD src tree <dev/ic/i8259.h> lacks some definitions.
85 */
86#define PIC_OCW1 1
87#define PIC_OCW2 0
88#define PIC_OCW3 0
89
90#define OCW2_SELECT 0
91#define OCW2_ILS(x) ((x) << 0) /* interrupt level select */
92
93#define OCW3_POLL_IRQ(x) ((x) & 0x7f)
94#define OCW3_POLL_PENDING (1U << 7)
95
96/*
97 * Galileo controller's registers are LE so convert to then
98 * to/from native byte order. We rely on boot loader or emulator
99 * to set "swap bytes" configuration correctly for us
100 */
101#define GT_PCI_DATA(v) htole32((v))
102#define GT_HOST_DATA(v) le32toh((v))
103
104struct gt_pci_softc;
105
106struct gt_pci_intr_cookie {
107 int irq;
108 struct gt_pci_softc *sc;
109};
110
111struct gt_pci_softc {
112 device_t sc_dev;
113 bus_space_tag_t sc_st;
114 bus_space_handle_t sc_ioh_icu1;
115 bus_space_handle_t sc_ioh_icu2;
116 bus_space_handle_t sc_ioh_elcr;
117
118 int sc_busno;
119 struct rman sc_mem_rman;
120 struct rman sc_io_rman;
121 struct rman sc_irq_rman;
122 unsigned long sc_mem;
123 bus_space_handle_t sc_io;
124
125 struct resource *sc_irq;
126 struct intr_event *sc_eventstab[ICU_LEN];
127 struct gt_pci_intr_cookie sc_intr_cookies[ICU_LEN];
128 uint16_t sc_imask;
129 uint16_t sc_elcr;
130
131 uint16_t sc_reserved;
132
133 void *sc_ih;
134};
135
136static void gt_pci_set_icus(struct gt_pci_softc *);
137static int gt_pci_intr(void *v);
138static int gt_pci_probe(device_t);
139static int gt_pci_attach(device_t);
140static int gt_pci_activate_resource(device_t, device_t, int, int,
141 struct resource *);
142static int gt_pci_setup_intr(device_t, device_t, struct resource *,
143 int, driver_filter_t *, driver_intr_t *, void *, void **);
144static int gt_pci_teardown_intr(device_t, device_t, struct resource *, void*);
145static int gt_pci_maxslots(device_t );
146static int gt_pci_conf_setup(struct gt_pci_softc *, int, int, int, int,
147 uint32_t *);
148static uint32_t gt_pci_read_config(device_t, u_int, u_int, u_int, u_int, int);
149static void gt_pci_write_config(device_t, u_int, u_int, u_int, u_int,
150 uint32_t, int);
151static int gt_pci_route_interrupt(device_t pcib, device_t dev, int pin);
152static struct resource * gt_pci_alloc_resource(device_t, device_t, int,
153 int *, u_long, u_long, u_long, u_int);
154
155static void
156gt_pci_mask_irq(void *source)
157{
158 struct gt_pci_intr_cookie *cookie = source;
159 struct gt_pci_softc *sc = cookie->sc;
160 int irq = cookie->irq;
161
162 sc->sc_imask |= (1 << irq);
163 sc->sc_elcr |= (1 << irq);
164
165 gt_pci_set_icus(sc);
166}
167
168static void
169gt_pci_unmask_irq(void *source)
170{
171 struct gt_pci_intr_cookie *cookie = source;
172 struct gt_pci_softc *sc = cookie->sc;
173 int irq = cookie->irq;
174
175 /* Enable it, set trigger mode. */
176 sc->sc_imask &= ~(1 << irq);
177 sc->sc_elcr &= ~(1 << irq);
178
179 gt_pci_set_icus(sc);
180}
181
182static void
183gt_pci_set_icus(struct gt_pci_softc *sc)
184{
185 /* Enable the cascade IRQ (2) if 8-15 is enabled. */
186 if ((sc->sc_imask & 0xff00) != 0xff00)
187 sc->sc_imask &= ~(1U << 2);
188 else
189 sc->sc_imask |= (1U << 2);
190
191 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW1,
192 sc->sc_imask & 0xff);
193 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, PIC_OCW1,
194 (sc->sc_imask >> 8) & 0xff);
195
196 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
197 sc->sc_elcr & 0xff);
198 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
199 (sc->sc_elcr >> 8) & 0xff);
200}
201
202static int
203gt_pci_intr(void *v)
204{
205 struct gt_pci_softc *sc = v;
206 struct intr_event *event;
207 int irq;
208
209 for (;;) {
210 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3,
211 OCW3_SEL | OCW3_P);
212 irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3);
213 if ((irq & OCW3_POLL_PENDING) == 0)
214 {
215 return FILTER_HANDLED;
216 }
217
218 irq = OCW3_POLL_IRQ(irq);
219
220 if (irq == 2) {
221 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
222 PIC_OCW3, OCW3_SEL | OCW3_P);
223 irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu2,
224 PIC_OCW3);
225 if (irq & OCW3_POLL_PENDING)
226 irq = OCW3_POLL_IRQ(irq) + 8;
227 else
228 irq = 2;
229 }
230
231 event = sc->sc_eventstab[irq];
232
233 if (!event || TAILQ_EMPTY(&event->ie_handlers))
234 continue;
235
236 /* TODO: frame instead of NULL? */
237 intr_event_handle(event, NULL);
238 /* XXX: Log stray IRQs */
239
240 /* Send a specific EOI to the 8259. */
241 if (irq > 7) {
242 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
243 PIC_OCW2, OCW2_SELECT | OCW2_EOI | OCW2_SL |
244 OCW2_ILS(irq & 7));
245 irq = 2;
246 }
247
248 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW2,
249 OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(irq));
250 }
251
252 return FILTER_HANDLED;
253}
254
255static int
256gt_pci_probe(device_t dev)
257{
258 device_set_desc(dev, "GT64120 PCI bridge");
259 return (0);
260}
261
262static int
263gt_pci_attach(device_t dev)
264{
265
266 uint32_t busno;
267 struct gt_pci_softc *sc = device_get_softc(dev);
268 int rid;
269
270 busno = 0;
271 sc->sc_dev = dev;
272 sc->sc_busno = busno;
273 sc->sc_st = mips_bus_space_generic;
274
275 /* Use KSEG1 to access IO ports for it is uncached */
276 sc->sc_io = MIPS_PHYS_TO_KSEG1(MALTA_PCI0_IO_BASE);
277 sc->sc_io_rman.rm_type = RMAN_ARRAY;
278 sc->sc_io_rman.rm_descr = "GT64120 PCI I/O Ports";
279 /*
280 * First 256 bytes are ISA's registers: e.g. i8259's
281 * So do not use them for general purpose PCI I/O window
282 */
283 if (rman_init(&sc->sc_io_rman) != 0 ||
284 rman_manage_region(&sc->sc_io_rman, 0x100, 0xffff) != 0) {
285 panic("gt_pci_attach: failed to set up I/O rman");
286 }
287
288 /* Use KSEG1 to access PCI memory for it is uncached */
289 sc->sc_mem = MIPS_PHYS_TO_KSEG1(MALTA_PCIMEM1_BASE);
290 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
291 sc->sc_mem_rman.rm_descr = "GT64120 PCI Memory";
292 if (rman_init(&sc->sc_mem_rman) != 0 ||
293 rman_manage_region(&sc->sc_mem_rman,
294 sc->sc_mem, sc->sc_mem + MALTA_PCIMEM1_SIZE) != 0) {
295 panic("gt_pci_attach: failed to set up memory rman");
296 }
297 sc->sc_irq_rman.rm_type = RMAN_ARRAY;
298 sc->sc_irq_rman.rm_descr = "GT64120 PCI IRQs";
299 if (rman_init(&sc->sc_irq_rman) != 0 ||
300 rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0)
301 panic("gt_pci_attach: failed to set up IRQ rman");
302
303 /*
304 * Map the PIC/ELCR registers.
305 */
306#if 0
307 if (bus_space_map(sc->sc_st, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0)
308 device_printf(dev, "unable to map ELCR registers\n");
309 if (bus_space_map(sc->sc_st, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)
310 device_printf(dev, "unable to map ICU1 registers\n");
311 if (bus_space_map(sc->sc_st, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)
312 device_printf(dev, "unable to map ICU2 registers\n");
313#else
314 sc->sc_ioh_elcr = sc->sc_io + 0x4d0;
315 sc->sc_ioh_icu1 = sc->sc_io + IO_ICU1;
316 sc->sc_ioh_icu2 = sc->sc_io + IO_ICU2;
317#endif
318
319
320 /* All interrupts default to "masked off". */
321 sc->sc_imask = 0xffff;
322
323 /* All interrupts default to edge-triggered. */
324 sc->sc_elcr = 0;
325
326 /*
327 * Initialize the 8259s.
328 */
329 /* reset, program device, 4 bytes */
330 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
331 ICW1_RESET | ICW1_IC4);
332 /*
333 * XXX: values from NetBSD's <dev/ic/i8259reg.h>
334 */
335 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
336 0/*XXX*/);
337 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
338 1 << 2);
339 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
340 ICW4_8086);
341
342 /* mask all interrupts */
343 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
344 sc->sc_imask & 0xff);
345
346 /* enable special mask mode */
347 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
348 OCW3_SEL | OCW3_ESMM | OCW3_SMM);
349
350 /* read IRR by default */
351 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
352 OCW3_SEL | OCW3_RR);
353
354 /* reset, program device, 4 bytes */
355 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
356 ICW1_RESET | ICW1_IC4);
357 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
358 0/*XXX*/);
359 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
360 1 << 2);
361 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
362 ICW4_8086);
363
364 /* mask all interrupts */
365 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
366 sc->sc_imask & 0xff);
367
368 /* enable special mask mode */
369 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
370 OCW3_SEL | OCW3_ESMM | OCW3_SMM);
371
372 /* read IRR by default */
373 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
374 OCW3_SEL | OCW3_RR);
375
376 /*
377 * Default all interrupts to edge-triggered.
378 */
379 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
380 sc->sc_elcr & 0xff);
381 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
382 (sc->sc_elcr >> 8) & 0xff);
383
384 /*
385 * Some ISA interrupts are reserved for devices that
386 * we know are hard-wired to certain IRQs.
387 */
388 sc->sc_reserved =
389 (1U << 0) | /* timer */
390 (1U << 1) | /* keyboard controller (keyboard) */
391 (1U << 2) | /* PIC cascade */
392 (1U << 3) | /* COM 2 */
393 (1U << 4) | /* COM 1 */
394 (1U << 6) | /* floppy */
395 (1U << 7) | /* centronics */
396 (1U << 8) | /* RTC */
397 (1U << 9) | /* I2C */
398 (1U << 12) | /* keyboard controller (mouse) */
399 (1U << 14) | /* IDE primary */
400 (1U << 15); /* IDE secondary */
401
402 /* Hook up our interrupt handler. */
403 if ((sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
404 MALTA_SOUTHBRIDGE_INTR, MALTA_SOUTHBRIDGE_INTR, 1,
405 RF_SHAREABLE | RF_ACTIVE)) == NULL) {
406 device_printf(dev, "unable to allocate IRQ resource\n");
407 return ENXIO;
408 }
409
410 if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC,
411 gt_pci_intr, NULL, sc, &sc->sc_ih))) {
412 device_printf(dev,
413 "WARNING: unable to register interrupt handler\n");
414 return ENXIO;
415 }
416
417 /* Initialize memory and i/o rmans. */
|
418 device_add_child(dev, "pci", busno);
| 418 device_add_child(dev, "pci", -1);
|
419 return (bus_generic_attach(dev));
420}
421
422static int
423gt_pci_maxslots(device_t dev)
424{
425 return (PCI_SLOTMAX);
426}
427
428static int
429gt_pci_conf_setup(struct gt_pci_softc *sc, int bus, int slot, int func,
430 int reg, uint32_t *addr)
431{
432 *addr = (bus << 16) | (slot << 11) | (func << 8) | reg;
433
434 return (0);
435}
436
437static uint32_t
438gt_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
439 int bytes)
440{
441 struct gt_pci_softc *sc = device_get_softc(dev);
442 uint32_t data;
443 uint32_t addr;
444 uint32_t shift, mask;
445
446 if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
447 return (uint32_t)(-1);
448
449 /* Clear cause register bits. */
450 GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0);
451 GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr);
452 /*
453 * Galileo system controller is special
454 */
455 if ((bus == 0) && (slot == 0))
456 data = GT_PCI_DATA(GT_REGVAL(GT_PCI0_CFG_DATA));
457 else
458 data = GT_REGVAL(GT_PCI0_CFG_DATA);
459
460 /* Check for master abort. */
461 if (GT_HOST_DATA(GT_REGVAL(GT_INTR_CAUSE)) & (GTIC_MASABORT0 | GTIC_TARABORT0))
462 data = (uint32_t) -1;
463
464 switch(reg % 4)
465 {
466 case 3:
467 shift = 24;
468 break;
469 case 2:
470 shift = 16;
471 break;
472 case 1:
473 shift = 8;
474 break;
475 default:
476 shift = 0;
477 break;
478 }
479
480 switch(bytes)
481 {
482 case 1:
483 mask = 0xff;
484 data = (data >> shift) & mask;
485 break;
486 case 2:
487 mask = 0xffff;
488 if(reg % 4 == 0)
489 data = data & mask;
490 else
491 data = (data >> 16) & mask;
492 break;
493 case 4:
494 break;
495 default:
496 panic("gt_pci_readconfig: wrong bytes count");
497 break;
498 }
499#if 0
500 printf("PCICONF_READ(%02x:%02x.%02x[%04x] -> %02x(%d)\n",
501 bus, slot, func, reg, data, bytes);
502#endif
503
504 return (data);
505}
506
507static void
508gt_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
509 uint32_t data, int bytes)
510{
511 struct gt_pci_softc *sc = device_get_softc(dev);
512 uint32_t addr;
513 uint32_t reg_data;
514 uint32_t shift, mask;
515
516 if(bytes != 4)
517 {
518 reg_data = gt_pci_read_config(dev, bus, slot, func, reg, 4);
519
520 shift = 8 * (reg & 3);
521
522 switch(bytes)
523 {
524 case 1:
525 mask = 0xff;
526 data = (reg_data & ~ (mask << shift)) | (data << shift);
527 break;
528 case 2:
529 mask = 0xffff;
530 if(reg % 4 == 0)
531 data = (reg_data & ~mask) | data;
532 else
533 data = (reg_data & ~ (mask << shift)) |
534 (data << shift);
535 break;
536 case 4:
537 break;
538 default:
539 panic("gt_pci_readconfig: wrong bytes count");
540 break;
541 }
542 }
543
544 if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
545 return;
546
547 /* The galileo has problems accessing device 31. */
548 if (bus == 0 && slot == 31)
549 return;
550
551 /* XXX: no support for bus > 0 yet */
552 if (bus > 0)
553 return;
554
555 /* Clear cause register bits. */
556 GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0);
557
558 GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr);
559
560 /*
561 * Galileo system controller is special
562 */
563 if ((bus == 0) && (slot == 0))
564 GT_REGVAL(GT_PCI0_CFG_DATA) = GT_PCI_DATA(data);
565 else
566 GT_REGVAL(GT_PCI0_CFG_DATA) = data;
567
568#if 0
569 printf("PCICONF_WRITE(%02x:%02x.%02x[%04x] -> %02x(%d)\n",
570 bus, slot, func, reg, data, bytes);
571#endif
572
573}
574
575static int
576gt_pci_route_interrupt(device_t pcib, device_t dev, int pin)
577{
578 int bus;
579 int device;
580 int func;
581 /* struct gt_pci_softc *sc = device_get_softc(pcib); */
582 bus = pci_get_bus(dev);
583 device = pci_get_slot(dev);
584 func = pci_get_function(dev);
585 /*
586 * XXXMIPS: We need routing logic. This is just a stub .
587 */
588 switch (device) {
589 case 9: /*
590 * PIIX4 IDE adapter. HW IRQ0
591 */
592 return 0;
593 case 11: /* Ethernet */
594 return 10;
595 default:
596 device_printf(pcib, "no IRQ mapping for %d/%d/%d/%d\n", bus, device, func, pin);
597
598 }
599 return (0);
600
601}
602
603static int
604gt_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
605{
606 struct gt_pci_softc *sc = device_get_softc(dev);
607 switch (which) {
608 case PCIB_IVAR_DOMAIN:
609 *result = 0;
610 return (0);
611 case PCIB_IVAR_BUS:
612 *result = sc->sc_busno;
613 return (0);
614
615 }
616 return (ENOENT);
617}
618
619static int
620gt_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
621{
622 struct gt_pci_softc * sc = device_get_softc(dev);
623
624 switch (which) {
625 case PCIB_IVAR_BUS:
626 sc->sc_busno = result;
627 return (0);
628 }
629 return (ENOENT);
630}
631
632static struct resource *
633gt_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
634 u_long start, u_long end, u_long count, u_int flags)
635{
636 struct gt_pci_softc *sc = device_get_softc(bus);
637 struct resource *rv = NULL;
638 struct rman *rm;
639 bus_space_handle_t bh = 0;
640
641 switch (type) {
642 case SYS_RES_IRQ:
643 rm = &sc->sc_irq_rman;
644 break;
645 case SYS_RES_MEMORY:
646 rm = &sc->sc_mem_rman;
647 bh = sc->sc_mem;
648 break;
649 case SYS_RES_IOPORT:
650 rm = &sc->sc_io_rman;
651 bh = sc->sc_io;
652 break;
653 default:
654 return (NULL);
655 }
656
657 rv = rman_reserve_resource(rm, start, end, count, flags, child);
658 if (rv == NULL)
659 return (NULL);
660 rman_set_rid(rv, *rid);
661 if (type != SYS_RES_IRQ) {
662 bh += (rman_get_start(rv));
663
664 rman_set_bustag(rv, gt_pci_bus_space);
665 rman_set_bushandle(rv, bh);
666 if (flags & RF_ACTIVE) {
667 if (bus_activate_resource(child, type, *rid, rv)) {
668 rman_release_resource(rv);
669 return (NULL);
670 }
671 }
672 }
673 return (rv);
674}
675
676static int
677gt_pci_activate_resource(device_t bus, device_t child, int type, int rid,
678 struct resource *r)
679{
680 bus_space_handle_t p;
681 int error;
682
683 if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) {
684 error = bus_space_map(rman_get_bustag(r),
685 rman_get_bushandle(r), rman_get_size(r), 0, &p);
686 if (error)
687 return (error);
688 rman_set_bushandle(r, p);
689 }
690 return (rman_activate_resource(r));
691}
692
693static int
694gt_pci_setup_intr(device_t dev, device_t child, struct resource *ires,
695 int flags, driver_filter_t *filt, driver_intr_t *handler,
696 void *arg, void **cookiep)
697{
698 struct gt_pci_softc *sc = device_get_softc(dev);
699 struct intr_event *event;
700 int irq, error;
701
702 irq = rman_get_start(ires);
703 if (irq >= ICU_LEN || irq == 2)
704 panic("%s: bad irq or type", __func__);
705
706 event = sc->sc_eventstab[irq];
707 sc->sc_intr_cookies[irq].irq = irq;
708 sc->sc_intr_cookies[irq].sc = sc;
709 if (event == NULL) {
710 error = intr_event_create(&event,
711 (void *)&sc->sc_intr_cookies[irq], 0, irq,
712 gt_pci_mask_irq, gt_pci_unmask_irq,
713 NULL, NULL, "gt_pci intr%d:", irq);
714 if (error)
715 return 0;
716 sc->sc_eventstab[irq] = event;
717 }
718
719 intr_event_add_handler(event, device_get_nameunit(child), filt,
720 handler, arg, intr_priority(flags), flags, cookiep);
721
722 gt_pci_unmask_irq((void *)&sc->sc_intr_cookies[irq]);
723 return 0;
724}
725
726static int
727gt_pci_teardown_intr(device_t dev, device_t child, struct resource *res,
728 void *cookie)
729{
730 struct gt_pci_softc *sc = device_get_softc(dev);
731 int irq;
732
733 irq = rman_get_start(res);
734 gt_pci_mask_irq((void *)&sc->sc_intr_cookies[irq]);
735
736 return (intr_event_remove_handler(cookie));
737}
738
739static device_method_t gt_pci_methods[] = {
740 /* Device interface */
741 DEVMETHOD(device_probe, gt_pci_probe),
742 DEVMETHOD(device_attach, gt_pci_attach),
743 DEVMETHOD(device_shutdown, bus_generic_shutdown),
744 DEVMETHOD(device_suspend, bus_generic_suspend),
745 DEVMETHOD(device_resume, bus_generic_resume),
746
747 /* Bus interface */
748 DEVMETHOD(bus_read_ivar, gt_read_ivar),
749 DEVMETHOD(bus_write_ivar, gt_write_ivar),
750 DEVMETHOD(bus_alloc_resource, gt_pci_alloc_resource),
751 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
752 DEVMETHOD(bus_activate_resource, gt_pci_activate_resource),
753 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
754 DEVMETHOD(bus_setup_intr, gt_pci_setup_intr),
755 DEVMETHOD(bus_teardown_intr, gt_pci_teardown_intr),
756
757 /* pcib interface */
758 DEVMETHOD(pcib_maxslots, gt_pci_maxslots),
759 DEVMETHOD(pcib_read_config, gt_pci_read_config),
760 DEVMETHOD(pcib_write_config, gt_pci_write_config),
761 DEVMETHOD(pcib_route_interrupt, gt_pci_route_interrupt),
762
763 DEVMETHOD_END
764};
765
766static driver_t gt_pci_driver = {
767 "pcib",
768 gt_pci_methods,
769 sizeof(struct gt_pci_softc),
770};
771
772static devclass_t gt_pci_devclass;
773
774DRIVER_MODULE(gt_pci, gt, gt_pci_driver, gt_pci_devclass, 0, 0);
| 419 return (bus_generic_attach(dev));
420}
421
422static int
423gt_pci_maxslots(device_t dev)
424{
425 return (PCI_SLOTMAX);
426}
427
428static int
429gt_pci_conf_setup(struct gt_pci_softc *sc, int bus, int slot, int func,
430 int reg, uint32_t *addr)
431{
432 *addr = (bus << 16) | (slot << 11) | (func << 8) | reg;
433
434 return (0);
435}
436
437static uint32_t
438gt_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
439 int bytes)
440{
441 struct gt_pci_softc *sc = device_get_softc(dev);
442 uint32_t data;
443 uint32_t addr;
444 uint32_t shift, mask;
445
446 if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
447 return (uint32_t)(-1);
448
449 /* Clear cause register bits. */
450 GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0);
451 GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr);
452 /*
453 * Galileo system controller is special
454 */
455 if ((bus == 0) && (slot == 0))
456 data = GT_PCI_DATA(GT_REGVAL(GT_PCI0_CFG_DATA));
457 else
458 data = GT_REGVAL(GT_PCI0_CFG_DATA);
459
460 /* Check for master abort. */
461 if (GT_HOST_DATA(GT_REGVAL(GT_INTR_CAUSE)) & (GTIC_MASABORT0 | GTIC_TARABORT0))
462 data = (uint32_t) -1;
463
464 switch(reg % 4)
465 {
466 case 3:
467 shift = 24;
468 break;
469 case 2:
470 shift = 16;
471 break;
472 case 1:
473 shift = 8;
474 break;
475 default:
476 shift = 0;
477 break;
478 }
479
480 switch(bytes)
481 {
482 case 1:
483 mask = 0xff;
484 data = (data >> shift) & mask;
485 break;
486 case 2:
487 mask = 0xffff;
488 if(reg % 4 == 0)
489 data = data & mask;
490 else
491 data = (data >> 16) & mask;
492 break;
493 case 4:
494 break;
495 default:
496 panic("gt_pci_readconfig: wrong bytes count");
497 break;
498 }
499#if 0
500 printf("PCICONF_READ(%02x:%02x.%02x[%04x] -> %02x(%d)\n",
501 bus, slot, func, reg, data, bytes);
502#endif
503
504 return (data);
505}
506
507static void
508gt_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
509 uint32_t data, int bytes)
510{
511 struct gt_pci_softc *sc = device_get_softc(dev);
512 uint32_t addr;
513 uint32_t reg_data;
514 uint32_t shift, mask;
515
516 if(bytes != 4)
517 {
518 reg_data = gt_pci_read_config(dev, bus, slot, func, reg, 4);
519
520 shift = 8 * (reg & 3);
521
522 switch(bytes)
523 {
524 case 1:
525 mask = 0xff;
526 data = (reg_data & ~ (mask << shift)) | (data << shift);
527 break;
528 case 2:
529 mask = 0xffff;
530 if(reg % 4 == 0)
531 data = (reg_data & ~mask) | data;
532 else
533 data = (reg_data & ~ (mask << shift)) |
534 (data << shift);
535 break;
536 case 4:
537 break;
538 default:
539 panic("gt_pci_readconfig: wrong bytes count");
540 break;
541 }
542 }
543
544 if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
545 return;
546
547 /* The galileo has problems accessing device 31. */
548 if (bus == 0 && slot == 31)
549 return;
550
551 /* XXX: no support for bus > 0 yet */
552 if (bus > 0)
553 return;
554
555 /* Clear cause register bits. */
556 GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0);
557
558 GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr);
559
560 /*
561 * Galileo system controller is special
562 */
563 if ((bus == 0) && (slot == 0))
564 GT_REGVAL(GT_PCI0_CFG_DATA) = GT_PCI_DATA(data);
565 else
566 GT_REGVAL(GT_PCI0_CFG_DATA) = data;
567
568#if 0
569 printf("PCICONF_WRITE(%02x:%02x.%02x[%04x] -> %02x(%d)\n",
570 bus, slot, func, reg, data, bytes);
571#endif
572
573}
574
575static int
576gt_pci_route_interrupt(device_t pcib, device_t dev, int pin)
577{
578 int bus;
579 int device;
580 int func;
581 /* struct gt_pci_softc *sc = device_get_softc(pcib); */
582 bus = pci_get_bus(dev);
583 device = pci_get_slot(dev);
584 func = pci_get_function(dev);
585 /*
586 * XXXMIPS: We need routing logic. This is just a stub .
587 */
588 switch (device) {
589 case 9: /*
590 * PIIX4 IDE adapter. HW IRQ0
591 */
592 return 0;
593 case 11: /* Ethernet */
594 return 10;
595 default:
596 device_printf(pcib, "no IRQ mapping for %d/%d/%d/%d\n", bus, device, func, pin);
597
598 }
599 return (0);
600
601}
602
603static int
604gt_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
605{
606 struct gt_pci_softc *sc = device_get_softc(dev);
607 switch (which) {
608 case PCIB_IVAR_DOMAIN:
609 *result = 0;
610 return (0);
611 case PCIB_IVAR_BUS:
612 *result = sc->sc_busno;
613 return (0);
614
615 }
616 return (ENOENT);
617}
618
619static int
620gt_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
621{
622 struct gt_pci_softc * sc = device_get_softc(dev);
623
624 switch (which) {
625 case PCIB_IVAR_BUS:
626 sc->sc_busno = result;
627 return (0);
628 }
629 return (ENOENT);
630}
631
632static struct resource *
633gt_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
634 u_long start, u_long end, u_long count, u_int flags)
635{
636 struct gt_pci_softc *sc = device_get_softc(bus);
637 struct resource *rv = NULL;
638 struct rman *rm;
639 bus_space_handle_t bh = 0;
640
641 switch (type) {
642 case SYS_RES_IRQ:
643 rm = &sc->sc_irq_rman;
644 break;
645 case SYS_RES_MEMORY:
646 rm = &sc->sc_mem_rman;
647 bh = sc->sc_mem;
648 break;
649 case SYS_RES_IOPORT:
650 rm = &sc->sc_io_rman;
651 bh = sc->sc_io;
652 break;
653 default:
654 return (NULL);
655 }
656
657 rv = rman_reserve_resource(rm, start, end, count, flags, child);
658 if (rv == NULL)
659 return (NULL);
660 rman_set_rid(rv, *rid);
661 if (type != SYS_RES_IRQ) {
662 bh += (rman_get_start(rv));
663
664 rman_set_bustag(rv, gt_pci_bus_space);
665 rman_set_bushandle(rv, bh);
666 if (flags & RF_ACTIVE) {
667 if (bus_activate_resource(child, type, *rid, rv)) {
668 rman_release_resource(rv);
669 return (NULL);
670 }
671 }
672 }
673 return (rv);
674}
675
676static int
677gt_pci_activate_resource(device_t bus, device_t child, int type, int rid,
678 struct resource *r)
679{
680 bus_space_handle_t p;
681 int error;
682
683 if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) {
684 error = bus_space_map(rman_get_bustag(r),
685 rman_get_bushandle(r), rman_get_size(r), 0, &p);
686 if (error)
687 return (error);
688 rman_set_bushandle(r, p);
689 }
690 return (rman_activate_resource(r));
691}
692
693static int
694gt_pci_setup_intr(device_t dev, device_t child, struct resource *ires,
695 int flags, driver_filter_t *filt, driver_intr_t *handler,
696 void *arg, void **cookiep)
697{
698 struct gt_pci_softc *sc = device_get_softc(dev);
699 struct intr_event *event;
700 int irq, error;
701
702 irq = rman_get_start(ires);
703 if (irq >= ICU_LEN || irq == 2)
704 panic("%s: bad irq or type", __func__);
705
706 event = sc->sc_eventstab[irq];
707 sc->sc_intr_cookies[irq].irq = irq;
708 sc->sc_intr_cookies[irq].sc = sc;
709 if (event == NULL) {
710 error = intr_event_create(&event,
711 (void *)&sc->sc_intr_cookies[irq], 0, irq,
712 gt_pci_mask_irq, gt_pci_unmask_irq,
713 NULL, NULL, "gt_pci intr%d:", irq);
714 if (error)
715 return 0;
716 sc->sc_eventstab[irq] = event;
717 }
718
719 intr_event_add_handler(event, device_get_nameunit(child), filt,
720 handler, arg, intr_priority(flags), flags, cookiep);
721
722 gt_pci_unmask_irq((void *)&sc->sc_intr_cookies[irq]);
723 return 0;
724}
725
726static int
727gt_pci_teardown_intr(device_t dev, device_t child, struct resource *res,
728 void *cookie)
729{
730 struct gt_pci_softc *sc = device_get_softc(dev);
731 int irq;
732
733 irq = rman_get_start(res);
734 gt_pci_mask_irq((void *)&sc->sc_intr_cookies[irq]);
735
736 return (intr_event_remove_handler(cookie));
737}
738
739static device_method_t gt_pci_methods[] = {
740 /* Device interface */
741 DEVMETHOD(device_probe, gt_pci_probe),
742 DEVMETHOD(device_attach, gt_pci_attach),
743 DEVMETHOD(device_shutdown, bus_generic_shutdown),
744 DEVMETHOD(device_suspend, bus_generic_suspend),
745 DEVMETHOD(device_resume, bus_generic_resume),
746
747 /* Bus interface */
748 DEVMETHOD(bus_read_ivar, gt_read_ivar),
749 DEVMETHOD(bus_write_ivar, gt_write_ivar),
750 DEVMETHOD(bus_alloc_resource, gt_pci_alloc_resource),
751 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
752 DEVMETHOD(bus_activate_resource, gt_pci_activate_resource),
753 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
754 DEVMETHOD(bus_setup_intr, gt_pci_setup_intr),
755 DEVMETHOD(bus_teardown_intr, gt_pci_teardown_intr),
756
757 /* pcib interface */
758 DEVMETHOD(pcib_maxslots, gt_pci_maxslots),
759 DEVMETHOD(pcib_read_config, gt_pci_read_config),
760 DEVMETHOD(pcib_write_config, gt_pci_write_config),
761 DEVMETHOD(pcib_route_interrupt, gt_pci_route_interrupt),
762
763 DEVMETHOD_END
764};
765
766static driver_t gt_pci_driver = {
767 "pcib",
768 gt_pci_methods,
769 sizeof(struct gt_pci_softc),
770};
771
772static devclass_t gt_pci_devclass;
773
774DRIVER_MODULE(gt_pci, gt, gt_pci_driver, gt_pci_devclass, 0, 0);
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