| cpuregs.h (274752) | cpuregs.h (290218) |
|---|---|
| 1/* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */ 2 3/* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. --- 38 unchanged lines hidden (view full) --- 47 * 48 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 49 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 51 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 52 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 53 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 54 * | 1/* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */ 2 3/* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. --- 38 unchanged lines hidden (view full) --- 47 * 48 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 49 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 51 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 52 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 53 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 54 * |
| 55 * $FreeBSD: head/sys/mips/include/cpuregs.h 274752 2014-11-20 17:06:41Z br $ | 55 * $FreeBSD: head/sys/mips/include/cpuregs.h 290218 2015-10-31 00:04:44Z adrian $ |
| 56 */ 57 58#ifndef _MIPS_CPUREGS_H_ 59#define _MIPS_CPUREGS_H_ 60 61/* 62 * Address space. 63 * 32-bit mips CPUS partition their 32-bit address space into four segments: --- 82 unchanged lines hidden (view full) --- 146#endif /* defined(CPU_R4000) || defined(CPU_R10000) */ 147 148#if defined(CPU_SB1) 149#define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */ 150#endif 151 152#if defined(CPU_MIPS74KC) 153#define MIPS_CCA_UNCACHED 0x02 | 56 */ 57 58#ifndef _MIPS_CPUREGS_H_ 59#define _MIPS_CPUREGS_H_ 60 61/* 62 * Address space. 63 * 32-bit mips CPUS partition their 32-bit address space into four segments: --- 82 unchanged lines hidden (view full) --- 146#endif /* defined(CPU_R4000) || defined(CPU_R10000) */ 147 148#if defined(CPU_SB1) 149#define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */ 150#endif 151 152#if defined(CPU_MIPS74KC) 153#define MIPS_CCA_UNCACHED 0x02 |
| 154#define MIPS_CCA_CACHED 0x00 | 154#define MIPS_CCA_CACHED 0x03 |
| 155#endif 156 157#ifndef MIPS_CCA_UNCACHED 158#define MIPS_CCA_UNCACHED MIPS_CCA_UC 159#endif 160 161/* 162 * If we don't know which cached mode to use and there is a cache coherent --- 475 unchanged lines hidden --- | 155#endif 156 157#ifndef MIPS_CCA_UNCACHED 158#define MIPS_CCA_UNCACHED MIPS_CCA_UC 159#endif 160 161/* 162 * If we don't know which cached mode to use and there is a cache coherent --- 475 unchanged lines hidden --- |