| cpuregs.h (256172) | cpuregs.h (274752) |
|---|---|
| 1/* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */ 2 3/* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. --- 38 unchanged lines hidden (view full) --- 47 * 48 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 49 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 51 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 52 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 53 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 54 * | 1/* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */ 2 3/* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. --- 38 unchanged lines hidden (view full) --- 47 * 48 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 49 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 51 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 52 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 53 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 54 * |
| 55 * $FreeBSD: head/sys/mips/include/cpuregs.h 256172 2013-10-09 00:27:12Z adrian $ | 55 * $FreeBSD: head/sys/mips/include/cpuregs.h 274752 2014-11-20 17:06:41Z br $ |
| 56 */ 57 58#ifndef _MIPS_CPUREGS_H_ 59#define _MIPS_CPUREGS_H_ 60 61/* 62 * Address space. 63 * 32-bit mips CPUS partition their 32-bit address space into four segments: --- 481 unchanged lines hidden (view full) --- 545#define MIPS_CONFIG1_C2 0x00000040 /* Coprocessor 2 implemented */ 546#define MIPS_CONFIG1_MD 0x00000020 /* MDMX ASE implemented (MIPS64) */ 547#define MIPS_CONFIG1_PC 0x00000010 /* Performance counters implemented */ 548#define MIPS_CONFIG1_WR 0x00000008 /* Watch registers implemented */ 549#define MIPS_CONFIG1_CA 0x00000004 /* MIPS16e ISA implemented */ 550#define MIPS_CONFIG1_EP 0x00000002 /* EJTAG implemented */ 551#define MIPS_CONFIG1_FP 0x00000001 /* FPU implemented */ 552 | 56 */ 57 58#ifndef _MIPS_CPUREGS_H_ 59#define _MIPS_CPUREGS_H_ 60 61/* 62 * Address space. 63 * 32-bit mips CPUS partition their 32-bit address space into four segments: --- 481 unchanged lines hidden (view full) --- 545#define MIPS_CONFIG1_C2 0x00000040 /* Coprocessor 2 implemented */ 546#define MIPS_CONFIG1_MD 0x00000020 /* MDMX ASE implemented (MIPS64) */ 547#define MIPS_CONFIG1_PC 0x00000010 /* Performance counters implemented */ 548#define MIPS_CONFIG1_WR 0x00000008 /* Watch registers implemented */ 549#define MIPS_CONFIG1_CA 0x00000004 /* MIPS16e ISA implemented */ 550#define MIPS_CONFIG1_EP 0x00000002 /* EJTAG implemented */ 551#define MIPS_CONFIG1_FP 0x00000001 /* FPU implemented */ 552 |
| 553#define MIPS_CONFIG2_SA_SHIFT 0 /* Secondary cache associativity */ 554#define MIPS_CONFIG2_SA_MASK 0xf 555#define MIPS_CONFIG2_SL_SHIFT 4 /* Secondary cache line size */ 556#define MIPS_CONFIG2_SL_MASK 0xf 557#define MIPS_CONFIG2_SS_SHIFT 8 /* Secondary cache sets per way */ 558#define MIPS_CONFIG2_SS_MASK 0xf 559 |
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| 553#define MIPS_CONFIG4_MMUSIZEEXT 0x000000FF /* bits 7.. 0 MMU Size Extension */ 554#define MIPS_CONFIG4_MMUEXTDEF 0x0000C000 /* bits 15.14 MMU Extension Definition */ 555#define MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT 0x00004000 /* This values denotes CONFIG4 bits */ 556 557/* 558 * Values for the code field in a break instruction. 559 */ 560#define MIPS_BREAK_INSTR 0x0000000d --- 70 unchanged lines hidden --- | 560#define MIPS_CONFIG4_MMUSIZEEXT 0x000000FF /* bits 7.. 0 MMU Size Extension */ 561#define MIPS_CONFIG4_MMUEXTDEF 0x0000C000 /* bits 15.14 MMU Extension Definition */ 562#define MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT 0x00004000 /* This values denotes CONFIG4 bits */ 563 564/* 565 * Values for the code field in a break instruction. 566 */ 567#define MIPS_BREAK_INSTR 0x0000000d --- 70 unchanged lines hidden --- |