1/*- 2 * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
26 * $FreeBSD: head/sys/mips/cavium/octeon_machdep.c 202831 2010-01-22 20:40:07Z imp $ |
27 */ 28#include <sys/cdefs.h> |
29__FBSDID("$FreeBSD: head/sys/mips/cavium/octeon_machdep.c 202831 2010-01-22 20:40:07Z imp $"); |
30 31#include <sys/param.h> 32#include <sys/conf.h> 33#include <sys/kernel.h> 34#include <sys/systm.h> 35#include <sys/imgact.h> 36#include <sys/bio.h> 37#include <sys/buf.h> --- 34 unchanged lines hidden (view full) --- 72#include <machine/vmparam.h> 73 74#if defined(__mips_n64) 75#define MAX_APP_DESC_ADDR 0xffffffffafffffff 76#else 77#define MAX_APP_DESC_ADDR 0xafffffff 78#endif 79 |
80static struct pcpu pcpu0; |
81extern int *edata; 82extern int *end; 83 84uint64_t ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip); 85void ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip); 86 87static void octeon_boot_params_init(register_t ptr); 88static uint64_t ciu_get_intr_sum_reg_addr(int core_num, int intx, int enx); 89static uint64_t ciu_get_intr_en_reg_addr(int core_num, int intx, int enx); 90 |
91static __inline void 92mips_wr_ebase(u_int32_t a0) 93{ 94 __asm __volatile("mtc0 %[a0], $15, 1 ;" 95 : 96 : [a0] "r"(a0)); 97 98 mips_barrier(); 99} 100 |
101void 102platform_cpu_init() 103{ 104 /* Nothing special yet */ 105} 106 107/* 108 * Perform a board-level soft-reset. --- 535 unchanged lines hidden (view full) --- 644#ifdef DEBUG_CIU_EN 645 printf(" Readback: 0x%llX\n\n ", 646 (uint64_t)oct_read64(ciu_intr_reg_addr)); 647#endif 648 649 octeon_set_interrupts(cpu_status_bits); 650} 651 |
652unsigned long 653octeon_get_clock_rate(void) 654{ 655 return octeon_cpu_clock; 656} 657 658static void 659octeon_memory_init(void) 660{ 661 uint32_t realmem_bytes; 662 663 if (octeon_board_real()) { 664 printf("octeon_dram == %llx\n", octeon_dram); 665 printf("reduced to ram: %u MB", (uint32_t) octeon_dram >> 20); 666 667 realmem_bytes = (octeon_dram - PAGE_SIZE); 668 realmem_bytes &= ~(PAGE_SIZE - 1); 669 printf("Real memory bytes is %x\n", realmem_bytes); 670 } else { 671 /* Simulator we limit to 96 meg */ 672 realmem_bytes = (96 << 20); 673 } 674 /* phys_avail regions are in bytes */ 675 phys_avail[0] = (MIPS_KSEG0_TO_PHYS((vm_offset_t)&end) + PAGE_SIZE) & ~(PAGE_SIZE - 1); 676 if (octeon_board_real()) { 677 if (realmem_bytes > OCTEON_DRAM_FIRST_256_END) 678 phys_avail[1] = OCTEON_DRAM_FIRST_256_END; 679 else 680 phys_avail[1] = realmem_bytes; 681 realmem_bytes -= OCTEON_DRAM_FIRST_256_END; 682 realmem_bytes &= ~(PAGE_SIZE - 1); 683 printf("phys_avail[0] = %x phys_avail[1] = %x\n", 684 phys_avail[0], phys_avail[1]); 685 } else { 686 /* Simulator gets 96Meg period. */ 687 phys_avail[1] = (96 << 20); 688 } 689 /*- 690 * Octeon Memory looks as follows: 691 * PA 692 * 0000 0000 to 0x0 0000 0000 0000 693 * 0FFF FFFF First 256 MB memory Maps to 0x0 0000 0FFF FFFF 694 * 695 * 1000 0000 to 0x1 0000 1000 0000 696 * 1FFF FFFF Uncached Bu I/O space.converted to 0x1 0000 1FFF FFFF 697 * 698 * 2FFF FFFF to Cached 0x0 0000 2000 0000 699 * FFFF FFFF all dram mem above the first 512M 0x3 FFFF FFFF FFFF 700 * 701 */ 702 physmem = btoc(phys_avail[1] - phys_avail[0]); 703 if ((octeon_board_real()) && 704 (realmem_bytes > OCTEON_DRAM_FIRST_256_END)) { 705 /* take out the upper non-cached 1/2 */ 706 realmem_bytes -= OCTEON_DRAM_FIRST_256_END; 707 realmem_bytes &= ~(PAGE_SIZE - 1); 708 /* Now map the rest of the memory */ 709 phys_avail[2] = 0x20000000; 710 printf("realmem_bytes is now at %x\n", realmem_bytes); 711 phys_avail[3] = ((uint32_t) 0x20000000 + realmem_bytes); 712 printf("Next block of memory goes from %x to %x\n", 713 phys_avail[2], phys_avail[3]); 714 physmem += btoc(phys_avail[3] - phys_avail[2]); 715 } else { 716 printf("realmem_bytes is %d\n", realmem_bytes); 717 } 718 realmem = physmem; 719 720 printf("\nTotal DRAM Size 0x%X", (uint32_t) octeon_dram); 721 printf("\nBank 0 = 0x%8X -> 0x%8X", phys_avail[0], phys_avail[1]); 722 printf("\nBank 1 = 0x%8X -> 0x%8X\n", phys_avail[2], phys_avail[3]); 723 printf("\nphysmem: 0x%lx", physmem); 724 725 Maxmem = physmem; 726 727} 728 |
729void 730platform_start(__register_t a0, __register_t a1, __register_t a2 __unused, 731 __register_t a3) 732{ 733 uint64_t platform_counter_freq; |
734 735 /* Initialize pcpu stuff */ 736 mips_pcpu0_init(); |
737 mips_timer_early_init(OCTEON_CLOCK_DEFAULT); 738 cninit(); |
739 |
740 octeon_ciu_reset(); |
741 octeon_boot_params_init(a3); |
742 bootverbose = 1; |
743 cpuid_to_pcpu[0] = &pcpu0; |
744 |
745 /* 746 * For some reason on the cn38xx simulator ebase register is set to 747 * 0x80001000 at bootup time. Move it back to the default, but 748 * when we move to having support for multiple executives, we need 749 * to rethink this. 750 */ 751 mips_wr_ebase(0x80000000); |
752 |
753 octeon_memory_init(); |
754 init_param1(); |
755 init_param2(physmem); 756 mips_cpu_init(); |
757 pmap_bootstrap(); 758 mips_proc0_init(); |
759 mutex_init(); 760#ifdef DDB 761 kdb_init(); 762#endif |
763 platform_counter_freq = octeon_get_clock_rate(); 764 mips_timer_init_params(platform_counter_freq, 1); |
765} 766 |
767/* impSTART: This stuff should move back into the Cavium SDK */ |
768/* 769 **************************************************************************************** 770 * 771 * APP/BOOT DESCRIPTOR STUFF 772 * 773 **************************************************************************************** 774 */ 775 --- 88 unchanged lines hidden (view full) --- 864 865uint32_t octeon_cpu_clock; 866uint64_t octeon_dram; 867uint32_t octeon_bd_ver = 0, octeon_cvmx_bd_ver = 0, octeon_board_rev_major, octeon_board_rev_minor, octeon_board_type; 868uint8_t octeon_mac_addr[6] = { 0 }; 869int octeon_core_mask, octeon_mac_addr_count; 870int octeon_chip_rev_major = 0, octeon_chip_rev_minor = 0, octeon_chip_type = 0; 871 |
872static octeon_boot_descriptor_t *app_desc_ptr; 873static cvmx_bootinfo_t *cvmx_desc_ptr; 874 875#define OCTEON_BOARD_TYPE_NONE 0 876#define OCTEON_BOARD_TYPE_SIM 1 877 878#define OCTEON_CLOCK_MIN (100 * 1000 * 1000) 879#define OCTEON_CLOCK_MAX (800 * 1000 * 1000) --- 16 unchanged lines hidden (view full) --- 896octeon_process_app_desc_ver_unknown(void) 897{ 898 printf(" Unknown Boot-Descriptor: Using Defaults\n"); 899 900 octeon_cpu_clock = OCTEON_CLOCK_DEFAULT; 901 octeon_dram = OCTEON_DRAM_DEFAULT; 902 octeon_board_rev_major = octeon_board_rev_minor = octeon_board_type = 0; 903 octeon_core_mask = 1; |
904 octeon_chip_type = octeon_chip_rev_major = octeon_chip_rev_minor = 0; 905 octeon_mac_addr[0] = 0x00; octeon_mac_addr[1] = 0x0f; 906 octeon_mac_addr[2] = 0xb7; octeon_mac_addr[3] = 0x10; 907 octeon_mac_addr[4] = 0x09; octeon_mac_addr[5] = 0x06; 908 octeon_mac_addr_count = 1; 909} 910 911static int --- 6 unchanged lines hidden (view full) --- 918 return 1; 919 } 920 cvmx_desc_ptr = 921 (cvmx_bootinfo_t *)(intptr_t)app_desc_ptr->cvmx_desc_vaddr; 922 cvmx_desc_ptr = 923 (cvmx_bootinfo_t *) ((intptr_t)cvmx_desc_ptr | MIPS_KSEG0_START); 924 octeon_cvmx_bd_ver = (cvmx_desc_ptr->major_version * 100) + 925 cvmx_desc_ptr->minor_version; |
926 if (cvmx_desc_ptr->major_version != 1) { |
927 panic("Incompatible CVMX descriptor from bootloader: %d.%d %p\n", |
928 (int) cvmx_desc_ptr->major_version, 929 (int) cvmx_desc_ptr->minor_version, cvmx_desc_ptr); |
930 } 931 932 octeon_core_mask = cvmx_desc_ptr->core_mask; 933 octeon_cpu_clock = cvmx_desc_ptr->eclock_hz; 934 octeon_board_type = cvmx_desc_ptr->board_type; 935 octeon_board_rev_major = cvmx_desc_ptr->board_rev_major; 936 octeon_board_rev_minor = cvmx_desc_ptr->board_rev_minor; 937 octeon_chip_type = cvmx_desc_ptr->chip_type; --- 9 unchanged lines hidden (view full) --- 947 948 if (app_desc_ptr->dram_size > 16*1024*1024) 949 octeon_dram = (uint64_t)app_desc_ptr->dram_size; 950 else 951 octeon_dram = (uint64_t)app_desc_ptr->dram_size << 20; 952 return 0; 953} 954 |
955static void 956octeon_boot_params_init(register_t ptr) 957{ 958 int bad_desc = 1; |
959 |
960 if (ptr != 0 && ptr < MAX_APP_DESC_ADDR) { 961 app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr; 962 octeon_bd_ver = app_desc_ptr->desc_version; |
963 if (app_desc_ptr->desc_version == 6) |
964 bad_desc = octeon_process_app_desc_ver_6(); 965 } 966 if (bad_desc) 967 octeon_process_app_desc_ver_unknown(); 968 969 printf("Boot Descriptor Ver: %u -> %u/%u", 970 octeon_bd_ver, octeon_cvmx_bd_ver/100, octeon_cvmx_bd_ver%100); 971 printf(" CPU clock: %uMHz\n", octeon_cpu_clock/1000000); 972 printf(" Dram: %u MB", (uint32_t)(octeon_dram >> 20)); 973 printf(" Board Type: %u Revision: %u/%u\n", 974 octeon_board_type, octeon_board_rev_major, octeon_board_rev_minor); 975 printf(" Octeon Chip: %u Rev %u/%u", 976 octeon_chip_type, octeon_chip_rev_major, octeon_chip_rev_minor); 977 |
978 printf(" Mac Address %02X.%02X.%02X.%02X.%02X.%02X (%d)\n", 979 octeon_mac_addr[0], octeon_mac_addr[1], octeon_mac_addr[2], 980 octeon_mac_addr[3], octeon_mac_addr[4], octeon_mac_addr[5], 981 octeon_mac_addr_count); |
982} |
983/* impEND: This stuff should move back into the Cavium SDK */ |