| ethernet-mv88e61xx.c (213346) | ethernet-mv88e61xx.c (213762) |
|---|---|
| 1/*- 2 * Copyright (c) 2010 Juli Mallett <jmallett@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2010 Juli Mallett <jmallett@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/mips/cavium/octe/ethernet-mv88e61xx.c 213346 2010-10-02 05:43:17Z jmallett $ | 26 * $FreeBSD: head/sys/mips/cavium/octe/ethernet-mv88e61xx.c 213762 2010-10-13 09:17:44Z jmallett $ |
| 27 */ 28 29/* 30 * Interface to the Marvell 88E61XX SMI/MDIO. 31 */ 32 33#include <sys/cdefs.h> | 27 */ 28 29/* 30 * Interface to the Marvell 88E61XX SMI/MDIO. 31 */ 32 33#include <sys/cdefs.h> |
| 34__FBSDID("$FreeBSD: head/sys/mips/cavium/octe/ethernet-mv88e61xx.c 213346 2010-10-02 05:43:17Z jmallett $"); | 34__FBSDID("$FreeBSD: head/sys/mips/cavium/octe/ethernet-mv88e61xx.c 213762 2010-10-13 09:17:44Z jmallett $"); |
| 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/endian.h> 40#include <sys/kernel.h> 41#include <sys/mbuf.h> 42#include <sys/socket.h> 43 44#include <dev/mii/mii.h> 45 46#include <net/ethernet.h> 47#include <net/if.h> 48 49#include "wrapper-cvmx-includes.h" 50#include "ethernet-headers.h" 51 | 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39#include <sys/endian.h> 40#include <sys/kernel.h> 41#include <sys/mbuf.h> 42#include <sys/socket.h> 43 44#include <dev/mii/mii.h> 45 46#include <net/ethernet.h> 47#include <net/if.h> 48 49#include "wrapper-cvmx-includes.h" 50#include "ethernet-headers.h" 51 |
| 52#define MV88E61XX_SMI_PHY_SW 0x10 /* Switch PHY. */ 53 | |
| 54#define MV88E61XX_SMI_REG_CMD 0x00 /* Indirect command register. */ 55#define MV88E61XX_SMI_CMD_BUSY 0x8000 /* Busy bit. */ 56#define MV88E61XX_SMI_CMD_22 0x1000 /* Clause 22 (default 45.) */ 57#define MV88E61XX_SMI_CMD_READ 0x0800 /* Read command. */ 58#define MV88E61XX_SMI_CMD_WRITE 0x0400 /* Write command. */ 59#define MV88E61XX_SMI_CMD_PHY(phy) (((phy) & 0x1f) << 5) 60#define MV88E61XX_SMI_CMD_REG(reg) ((reg) & 0x1f) 61 62#define MV88E61XX_SMI_REG_DAT 0x01 /* Indirect data register. */ 63 | 52#define MV88E61XX_SMI_REG_CMD 0x00 /* Indirect command register. */ 53#define MV88E61XX_SMI_CMD_BUSY 0x8000 /* Busy bit. */ 54#define MV88E61XX_SMI_CMD_22 0x1000 /* Clause 22 (default 45.) */ 55#define MV88E61XX_SMI_CMD_READ 0x0800 /* Read command. */ 56#define MV88E61XX_SMI_CMD_WRITE 0x0400 /* Write command. */ 57#define MV88E61XX_SMI_CMD_PHY(phy) (((phy) & 0x1f) << 5) 58#define MV88E61XX_SMI_CMD_REG(reg) ((reg) & 0x1f) 59 60#define MV88E61XX_SMI_REG_DAT 0x01 /* Indirect data register. */ 61 |
| 64static int cvm_oct_mv88e61xx_mdio_read(struct ifnet *, int, int); 65static void cvm_oct_mv88e61xx_mdio_write(struct ifnet *, int, int, int); | |
| 66static int cvm_oct_mv88e61xx_smi_read(struct ifnet *, int, int); 67static void cvm_oct_mv88e61xx_smi_write(struct ifnet *, int, int, int); | 62static int cvm_oct_mv88e61xx_smi_read(struct ifnet *, int, int); 63static void cvm_oct_mv88e61xx_smi_write(struct ifnet *, int, int, int); |
| 68static int cvm_oct_mv88e61xx_smi_wait(struct ifnet *, int); | 64static int cvm_oct_mv88e61xx_smi_wait(struct ifnet *); |
| 69 70int 71cvm_oct_mv88e61xx_setup_device(struct ifnet *ifp) 72{ 73 cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc; 74 | 65 66int 67cvm_oct_mv88e61xx_setup_device(struct ifnet *ifp) 68{ 69 cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc; 70 |
| 75 priv->mdio_read = cvm_oct_mv88e61xx_mdio_read; 76 priv->mdio_write = cvm_oct_mv88e61xx_mdio_write; | 71 priv->mdio_read = cvm_oct_mv88e61xx_smi_read; 72 priv->mdio_write = cvm_oct_mv88e61xx_smi_write; 73 priv->phy_device = "mv88e61xxphy"; |
| 77 78 return (0); 79} 80 81static int | 74 75 return (0); 76} 77 78static int |
| 82cvm_oct_mv88e61xx_mdio_read(struct ifnet *ifp, int phy_id, int location) 83{ 84 /* 85 * Intercept reads of MII_BMSR. The miibus uses this to determine 86 * PHY presence and we only want it to look for a PHY attachment 87 * for the switch PHY itself. The PHY driver will talk to all of 88 * the other ports as need be. 89 */ 90 switch (location) { 91 case MII_BMSR: 92 if (phy_id != MV88E61XX_SMI_PHY_SW) 93 return (0); 94 return (BMSR_EXTSTAT | BMSR_ACOMP | BMSR_LINK); 95 default: 96 return (cvm_oct_mv88e61xx_smi_read(ifp, phy_id, location)); 97 } 98} 99 100static void 101cvm_oct_mv88e61xx_mdio_write(struct ifnet *ifp, int phy_id, int location, int val) 102{ 103 return (cvm_oct_mv88e61xx_smi_write(ifp, phy_id, location, val)); 104} 105 106static int | |
| 107cvm_oct_mv88e61xx_smi_read(struct ifnet *ifp, int phy_id, int location) 108{ | 79cvm_oct_mv88e61xx_smi_read(struct ifnet *ifp, int phy_id, int location) 80{ |
| 81 cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc; |
|
| 109 int error; 110 | 82 int error; 83 |
| 111 error = cvm_oct_mv88e61xx_smi_wait(ifp, phy_id); | 84 error = cvm_oct_mv88e61xx_smi_wait(ifp); |
| 112 if (error != 0) 113 return (0); 114 | 85 if (error != 0) 86 return (0); 87 |
| 115 cvm_oct_mdio_write(ifp, phy_id, MV88E61XX_SMI_REG_CMD, | 88 cvm_oct_mdio_write(ifp, priv->phy_id, MV88E61XX_SMI_REG_CMD, |
| 116 MV88E61XX_SMI_CMD_BUSY | MV88E61XX_SMI_CMD_22 | 117 MV88E61XX_SMI_CMD_READ | MV88E61XX_SMI_CMD_PHY(phy_id) | 118 MV88E61XX_SMI_CMD_REG(location)); 119 | 89 MV88E61XX_SMI_CMD_BUSY | MV88E61XX_SMI_CMD_22 | 90 MV88E61XX_SMI_CMD_READ | MV88E61XX_SMI_CMD_PHY(phy_id) | 91 MV88E61XX_SMI_CMD_REG(location)); 92 |
| 120 error = cvm_oct_mv88e61xx_smi_wait(ifp, phy_id); | 93 error = cvm_oct_mv88e61xx_smi_wait(ifp); |
| 121 if (error != 0) 122 return (0); 123 | 94 if (error != 0) 95 return (0); 96 |
| 124 return (cvm_oct_mdio_read(ifp, phy_id, MV88E61XX_SMI_REG_DAT)); | 97 return (cvm_oct_mdio_read(ifp, priv->phy_id, MV88E61XX_SMI_REG_DAT)); |
| 125} 126 127static void 128cvm_oct_mv88e61xx_smi_write(struct ifnet *ifp, int phy_id, int location, int val) 129{ | 98} 99 100static void 101cvm_oct_mv88e61xx_smi_write(struct ifnet *ifp, int phy_id, int location, int val) 102{ |
| 130 cvm_oct_mv88e61xx_smi_wait(ifp, phy_id); 131 cvm_oct_mdio_write(ifp, phy_id, MV88E61XX_SMI_REG_DAT, val); 132 cvm_oct_mdio_write(ifp, phy_id, MV88E61XX_SMI_REG_CMD, | 103 cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc; 104 105 cvm_oct_mv88e61xx_smi_wait(ifp); 106 cvm_oct_mdio_write(ifp, priv->phy_id, MV88E61XX_SMI_REG_DAT, val); 107 cvm_oct_mdio_write(ifp, priv->phy_id, MV88E61XX_SMI_REG_CMD, |
| 133 MV88E61XX_SMI_CMD_BUSY | MV88E61XX_SMI_CMD_22 | 134 MV88E61XX_SMI_CMD_WRITE | MV88E61XX_SMI_CMD_PHY(phy_id) | 135 MV88E61XX_SMI_CMD_REG(location)); | 108 MV88E61XX_SMI_CMD_BUSY | MV88E61XX_SMI_CMD_22 | 109 MV88E61XX_SMI_CMD_WRITE | MV88E61XX_SMI_CMD_PHY(phy_id) | 110 MV88E61XX_SMI_CMD_REG(location)); |
| 136 cvm_oct_mv88e61xx_smi_wait(ifp, phy_id); | 111 cvm_oct_mv88e61xx_smi_wait(ifp); |
| 137} 138 139static int | 112} 113 114static int |
| 140cvm_oct_mv88e61xx_smi_wait(struct ifnet *ifp, int phy_id) | 115cvm_oct_mv88e61xx_smi_wait(struct ifnet *ifp) |
| 141{ | 116{ |
| 117 cvm_oct_private_t *priv = (cvm_oct_private_t *)ifp->if_softc; |
|
| 142 uint16_t cmd; 143 unsigned i; 144 145 for (i = 0; i < 10000; i++) { | 118 uint16_t cmd; 119 unsigned i; 120 121 for (i = 0; i < 10000; i++) { |
| 146 cmd = cvm_oct_mdio_read(ifp, phy_id, MV88E61XX_SMI_REG_CMD); | 122 cmd = cvm_oct_mdio_read(ifp, priv->phy_id, MV88E61XX_SMI_REG_CMD); |
| 147 if ((cmd & MV88E61XX_SMI_CMD_BUSY) == 0) 148 return (0); 149 } 150 return (ETIMEDOUT); 151} | 123 if ((cmd & MV88E61XX_SMI_CMD_BUSY) == 0) 124 return (0); 125 } 126 return (ETIMEDOUT); 127} |