uart_cpu_ar71xx.c (191079) | uart_cpu_ar71xx.c (191289) |
---|---|
1/*- 2 * Copyright (c) 2009 Oleksandr Tymoshenko 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 25 unchanged lines hidden (view full) --- 34#include <sys/bus.h> 35 36#include <machine/bus.h> 37 38#include <dev/uart/uart.h> 39#include <dev/uart/uart_cpu.h> 40 41#include <mips/atheros/ar71xxreg.h> | 1/*- 2 * Copyright (c) 2009 Oleksandr Tymoshenko 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 25 unchanged lines hidden (view full) --- 34#include <sys/bus.h> 35 36#include <machine/bus.h> 37 38#include <dev/uart/uart.h> 39#include <dev/uart/uart_cpu.h> 40 41#include <mips/atheros/ar71xxreg.h> |
42#include <mips/atheros/ar71xx_bus_space_reversed.h> |
|
42 43bus_space_tag_t uart_bus_space_io; 44bus_space_tag_t uart_bus_space_mem; 45 46int 47uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) 48{ 49 return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); 50} 51 52int 53uart_cpu_getdev(int devtype, struct uart_devinfo *di) 54{ 55 di->ops = uart_getops(&uart_ns8250_class); 56 di->bas.chan = 0; | 43 44bus_space_tag_t uart_bus_space_io; 45bus_space_tag_t uart_bus_space_mem; 46 47int 48uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) 49{ 50 return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); 51} 52 53int 54uart_cpu_getdev(int devtype, struct uart_devinfo *di) 55{ 56 di->ops = uart_getops(&uart_ns8250_class); 57 di->bas.chan = 0; |
57 di->bas.bst = MIPS_BUS_SPACE_MEM; | 58 di->bas.bst = &ar71xx_bus_space_reversed; |
58 di->bas.regshft = 2; 59 /* TODO: calculate proper AHB freq using PLL registers */ 60 di->bas.rclk = 85000000; 61 di->baudrate = 115200; 62 di->databits = 8; 63 di->stopbits = 1; 64 di->parity = UART_PARITY_NONE; 65 66 /* TODO: check if uart_bus_space_io mandatory to set */ | 59 di->bas.regshft = 2; 60 /* TODO: calculate proper AHB freq using PLL registers */ 61 di->bas.rclk = 85000000; 62 di->baudrate = 115200; 63 di->databits = 8; 64 di->stopbits = 1; 65 di->parity = UART_PARITY_NONE; 66 67 /* TODO: check if uart_bus_space_io mandatory to set */ |
67 uart_bus_space_io = MIPS_BUS_SPACE_IO; 68 uart_bus_space_mem = MIPS_BUS_SPACE_MEM; | 68 uart_bus_space_io = NULL; 69 uart_bus_space_mem = &ar71xx_bus_space_reversed; |
69 /* 70 * FIXME: 71 * 3 is to compensate big endian, uart operates 72 * with bus_space_read_1/bus_space_write_1 and hence gets 73 * highest byte instead of lowest one. Actual fix will involve 74 * MIPS bus_space fixing. 75 */ | 70 /* 71 * FIXME: 72 * 3 is to compensate big endian, uart operates 73 * with bus_space_read_1/bus_space_write_1 and hence gets 74 * highest byte instead of lowest one. Actual fix will involve 75 * MIPS bus_space fixing. 76 */ |
76 di->bas.bsh = MIPS_PHYS_TO_KSEG1(AR71XX_UART_ADDR) + 3; | 77 di->bas.bsh = MIPS_PHYS_TO_KSEG1(AR71XX_UART_ADDR); |
77 return (0); 78} | 78 return (0); 79} |