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if_arge.c (285121) if_arge.c (289476)
1/*-
2 * Copyright (c) 2009, Oleksandr Tymoshenko
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 12 unchanged lines hidden (view full) ---

21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2009, Oleksandr Tymoshenko
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 12 unchanged lines hidden (view full) ---

21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/mips/atheros/if_arge.c 285121 2015-07-04 03:05:57Z adrian $");
29__FBSDID("$FreeBSD: head/sys/mips/atheros/if_arge.c 289476 2015-10-18 00:59:28Z adrian $");
30
31/*
32 * AR71XX gigabit ethernet driver
33 */
34#ifdef HAVE_KERNEL_OPTION_HEADERS
35#include "opt_device_polling.h"
36#endif
37

--- 255 unchanged lines hidden (view full) ---

293 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
294 "tx_pkts_aligned", CTLFLAG_RW, &sc->stats.tx_pkts_aligned, 0,
295 "number of TX aligned packets");
296
297 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
298 "tx_pkts_unaligned", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned,
299 0, "number of TX unaligned packets");
300
30
31/*
32 * AR71XX gigabit ethernet driver
33 */
34#ifdef HAVE_KERNEL_OPTION_HEADERS
35#include "opt_device_polling.h"
36#endif
37

--- 255 unchanged lines hidden (view full) ---

293 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
294 "tx_pkts_aligned", CTLFLAG_RW, &sc->stats.tx_pkts_aligned, 0,
295 "number of TX aligned packets");
296
297 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
298 "tx_pkts_unaligned", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned,
299 0, "number of TX unaligned packets");
300
301 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
302 "tx_pkts_unaligned_start", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned_start,
303 0, "number of TX unaligned packets (start)");
304
305 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
306 "tx_pkts_unaligned_len", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned_len,
307 0, "number of TX unaligned packets (len)");
308
309 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
310 "tx_pkts_nosegs", CTLFLAG_RW, &sc->stats.tx_pkts_nosegs,
311 0, "number of TX packets fail with no ring slots avail");
312
313 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
314 "intr_stray_filter", CTLFLAG_RW, &sc->stats.intr_stray,
315 0, "number of stray interrupts (filter)");
316
317 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
318 "intr_stray_intr", CTLFLAG_RW, &sc->stats.intr_stray2,
319 0, "number of stray interrupts (intr)");
320
321 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
322 "intr_ok", CTLFLAG_RW, &sc->stats.intr_ok,
323 0, "number of OK interrupts");
301#ifdef ARGE_DEBUG
302 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_prod",
303 CTLFLAG_RW, &sc->arge_cdata.arge_tx_prod, 0, "");
304 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cons",
305 CTLFLAG_RW, &sc->arge_cdata.arge_tx_cons, 0, "");
306 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cnt",
307 CTLFLAG_RW, &sc->arge_cdata.arge_tx_cnt, 0, "");
308#endif

--- 313 unchanged lines hidden (view full) ---

622 local_macaddr[i] = tmpmac[i];
623 }
624 /* Done! */
625 freeenv(local_macstr);
626 local_macstr = NULL;
627 }
628
629 /*
324#ifdef ARGE_DEBUG
325 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_prod",
326 CTLFLAG_RW, &sc->arge_cdata.arge_tx_prod, 0, "");
327 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cons",
328 CTLFLAG_RW, &sc->arge_cdata.arge_tx_cons, 0, "");
329 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cnt",
330 CTLFLAG_RW, &sc->arge_cdata.arge_tx_cnt, 0, "");
331#endif

--- 313 unchanged lines hidden (view full) ---

645 local_macaddr[i] = tmpmac[i];
646 }
647 /* Done! */
648 freeenv(local_macstr);
649 local_macstr = NULL;
650 }
651
652 /*
653 * Hardware workarounds.
654 */
655 switch (ar71xx_soc) {
656 case AR71XX_SOC_QCA9556:
657 case AR71XX_SOC_QCA9558:
658 /* Arbitrary alignment */
659 sc->arge_hw_flags |= ARGE_HW_FLG_TX_DESC_ALIGN_1BYTE;
660 sc->arge_hw_flags |= ARGE_HW_FLG_RX_DESC_ALIGN_1BYTE;
661 break;
662 default:
663 sc->arge_hw_flags |= ARGE_HW_FLG_TX_DESC_ALIGN_4BYTE;
664 sc->arge_hw_flags |= ARGE_HW_FLG_RX_DESC_ALIGN_4BYTE;
665 break;
666 }
667
668 /*
630 * Some units (eg the TP-Link WR-1043ND) do not have a convenient
631 * EEPROM location to read the ethernet MAC address from.
632 * OpenWRT simply snaffles it from a fixed location.
633 *
634 * Since multiple units seem to use this feature, include
635 * a method of setting the MAC address based on an flash location
636 * in CPU address space.
637 *

--- 182 unchanged lines hidden (view full) ---

820 | (sc->arge_eaddr[3] << 16) | (sc->arge_eaddr[4] << 8)
821 | sc->arge_eaddr[5]);
822 ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR2, (sc->arge_eaddr[0] << 8)
823 | sc->arge_eaddr[1]);
824
825 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0,
826 FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT);
827
669 * Some units (eg the TP-Link WR-1043ND) do not have a convenient
670 * EEPROM location to read the ethernet MAC address from.
671 * OpenWRT simply snaffles it from a fixed location.
672 *
673 * Since multiple units seem to use this feature, include
674 * a method of setting the MAC address based on an flash location
675 * in CPU address space.
676 *

--- 182 unchanged lines hidden (view full) ---

859 | (sc->arge_eaddr[3] << 16) | (sc->arge_eaddr[4] << 8)
860 | sc->arge_eaddr[5]);
861 ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR2, (sc->arge_eaddr[0] << 8)
862 | sc->arge_eaddr[1]);
863
864 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0,
865 FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT);
866
867 /*
868 * SoC specific bits.
869 */
828 switch (ar71xx_soc) {
829 case AR71XX_SOC_AR7240:
830 case AR71XX_SOC_AR7241:
831 case AR71XX_SOC_AR7242:
832 case AR71XX_SOC_AR9330:
833 case AR71XX_SOC_AR9331:
834 case AR71XX_SOC_AR9341:
835 case AR71XX_SOC_AR9342:

--- 510 unchanged lines hidden (view full) ---

1346 /* Enable interrupts */
1347 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
1348}
1349
1350/*
1351 * Return whether the mbuf chain is correctly aligned
1352 * for the arge TX engine.
1353 *
870 switch (ar71xx_soc) {
871 case AR71XX_SOC_AR7240:
872 case AR71XX_SOC_AR7241:
873 case AR71XX_SOC_AR7242:
874 case AR71XX_SOC_AR9330:
875 case AR71XX_SOC_AR9331:
876 case AR71XX_SOC_AR9341:
877 case AR71XX_SOC_AR9342:

--- 510 unchanged lines hidden (view full) ---

1388 /* Enable interrupts */
1389 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
1390}
1391
1392/*
1393 * Return whether the mbuf chain is correctly aligned
1394 * for the arge TX engine.
1395 *
1354 * The TX engine requires each fragment to be aligned to a
1355 * 4 byte boundary and the size of each fragment except
1356 * the last to be a multiple of 4 bytes.
1396 * All the MACs have a length requirement: any non-final
1397 * fragment (ie, descriptor with MORE bit set) needs to have
1398 * a length divisible by 4.
1357 *
1399 *
1358 * XXX TODO: I believe this is only a bug on the AR71xx and
1359 * AR913x MACs. The later MACs (AR724x and later) does not
1360 * need this workaround.
1400 * The AR71xx, AR913x require the start address also be
1401 * DWORD aligned. The later MACs don't.
1361 */
1362static int
1402 */
1403static int
1363arge_mbuf_chain_is_tx_aligned(struct mbuf *m0)
1404arge_mbuf_chain_is_tx_aligned(struct arge_softc *sc, struct mbuf *m0)
1364{
1365 struct mbuf *m;
1366
1367 for (m = m0; m != NULL; m = m->m_next) {
1405{
1406 struct mbuf *m;
1407
1408 for (m = m0; m != NULL; m = m->m_next) {
1368 if((mtod(m, intptr_t) & 3) != 0)
1409 /*
1410 * Only do this for chips that require it.
1411 */
1412 if ((sc->arge_hw_flags & ARGE_HW_FLG_TX_DESC_ALIGN_4BYTE) &&
1413 (mtod(m, intptr_t) & 3) != 0) {
1414 sc->stats.tx_pkts_unaligned_start++;
1369 return 0;
1415 return 0;
1370 if ((m->m_next != NULL) && ((m->m_len & 0x03) != 0))
1416 }
1417
1418 /*
1419 * All chips have this requirement for length.
1420 */
1421 if ((m->m_next != NULL) && ((m->m_len & 0x03) != 0)) {
1422 sc->stats.tx_pkts_unaligned_len++;
1371 return 0;
1423 return 0;
1424 }
1372 }
1373 return 1;
1374}
1375
1376/*
1377 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1378 * pointers to the fragment pointers.
1379 */

--- 4 unchanged lines hidden (view full) ---

1384 struct arge_desc *desc, *prev_desc;
1385 bus_dma_segment_t txsegs[ARGE_MAXFRAGS];
1386 int error, i, nsegs, prod, prev_prod;
1387 struct mbuf *m;
1388
1389 ARGE_LOCK_ASSERT(sc);
1390
1391 /*
1425 }
1426 return 1;
1427}
1428
1429/*
1430 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1431 * pointers to the fragment pointers.
1432 */

--- 4 unchanged lines hidden (view full) ---

1437 struct arge_desc *desc, *prev_desc;
1438 bus_dma_segment_t txsegs[ARGE_MAXFRAGS];
1439 int error, i, nsegs, prod, prev_prod;
1440 struct mbuf *m;
1441
1442 ARGE_LOCK_ASSERT(sc);
1443
1444 /*
1392 * Fix mbuf chain, all fragments should be 4 bytes aligned and
1393 * even 4 bytes
1394 *
1395 * XXX TODO: I believe this is only a bug on the AR71xx and
1396 * AR913x MACs. The later MACs (AR724x and later) does not
1397 * need this workaround.
1445 * Fix mbuf chain based on hardware alignment constraints.
1398 */
1399 m = *m_head;
1446 */
1447 m = *m_head;
1400 if (! arge_mbuf_chain_is_tx_aligned(m)) {
1448 if (! arge_mbuf_chain_is_tx_aligned(sc, m)) {
1401 sc->stats.tx_pkts_unaligned++;
1402 m = m_defrag(*m_head, M_NOWAIT);
1403 if (m == NULL) {
1404 *m_head = NULL;
1405 return (ENOBUFS);
1406 }
1407 *m_head = m;
1408 } else

--- 13 unchanged lines hidden (view full) ---

1422 m_freem(*m_head);
1423 *m_head = NULL;
1424 return (EIO);
1425 }
1426
1427 /* Check number of available descriptors. */
1428 if (sc->arge_cdata.arge_tx_cnt + nsegs >= (ARGE_TX_RING_COUNT - 1)) {
1429 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
1449 sc->stats.tx_pkts_unaligned++;
1450 m = m_defrag(*m_head, M_NOWAIT);
1451 if (m == NULL) {
1452 *m_head = NULL;
1453 return (ENOBUFS);
1454 }
1455 *m_head = m;
1456 } else

--- 13 unchanged lines hidden (view full) ---

1470 m_freem(*m_head);
1471 *m_head = NULL;
1472 return (EIO);
1473 }
1474
1475 /* Check number of available descriptors. */
1476 if (sc->arge_cdata.arge_tx_cnt + nsegs >= (ARGE_TX_RING_COUNT - 1)) {
1477 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
1478 sc->stats.tx_pkts_nosegs++;
1430 return (ENOBUFS);
1431 }
1432
1433 txd->tx_m = *m_head;
1434 bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
1435 BUS_DMASYNC_PREWRITE);
1436
1437 /*
1438 * Make a list of descriptors for this packet. DMA controller will
1439 * walk through it while arge_link is not zero.
1440 */
1441 prev_prod = prod;
1442 desc = prev_desc = NULL;
1443 for (i = 0; i < nsegs; i++) {
1444 desc = &sc->arge_rdata.arge_tx_ring[prod];
1445 desc->packet_ctrl = ARGE_DMASIZE(txsegs[i].ds_len);
1446
1479 return (ENOBUFS);
1480 }
1481
1482 txd->tx_m = *m_head;
1483 bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
1484 BUS_DMASYNC_PREWRITE);
1485
1486 /*
1487 * Make a list of descriptors for this packet. DMA controller will
1488 * walk through it while arge_link is not zero.
1489 */
1490 prev_prod = prod;
1491 desc = prev_desc = NULL;
1492 for (i = 0; i < nsegs; i++) {
1493 desc = &sc->arge_rdata.arge_tx_ring[prod];
1494 desc->packet_ctrl = ARGE_DMASIZE(txsegs[i].ds_len);
1495
1447 if (txsegs[i].ds_addr & 3)
1496 /* XXX Note: only relevant for older MACs; but check length! */
1497 if ((sc->arge_hw_flags & ARGE_HW_FLG_TX_DESC_ALIGN_4BYTE) &&
1498 (txsegs[i].ds_addr & 3))
1448 panic("TX packet address unaligned\n");
1449
1450 desc->packet_addr = txsegs[i].ds_addr;
1451
1452 /* link with previous descriptor */
1453 if (prev_desc)
1454 prev_desc->packet_ctrl |= ARGE_DESC_MORE;
1455

--- 254 unchanged lines hidden (view full) ---

1710
1711static int
1712arge_dma_alloc(struct arge_softc *sc)
1713{
1714 struct arge_dmamap_arg ctx;
1715 struct arge_txdesc *txd;
1716 struct arge_rxdesc *rxd;
1717 int error, i;
1499 panic("TX packet address unaligned\n");
1500
1501 desc->packet_addr = txsegs[i].ds_addr;
1502
1503 /* link with previous descriptor */
1504 if (prev_desc)
1505 prev_desc->packet_ctrl |= ARGE_DESC_MORE;
1506

--- 254 unchanged lines hidden (view full) ---

1761
1762static int
1763arge_dma_alloc(struct arge_softc *sc)
1764{
1765 struct arge_dmamap_arg ctx;
1766 struct arge_txdesc *txd;
1767 struct arge_rxdesc *rxd;
1768 int error, i;
1769 int arge_tx_align, arge_rx_align;
1718
1770
1771 /* Assume 4 byte alignment by default */
1772 arge_tx_align = 4;
1773 arge_rx_align = 4;
1774
1775 if (sc->arge_hw_flags & ARGE_HW_FLG_TX_DESC_ALIGN_1BYTE)
1776 arge_tx_align = 1;
1777 if (sc->arge_hw_flags & ARGE_HW_FLG_RX_DESC_ALIGN_1BYTE)
1778 arge_rx_align = 1;
1779
1719 /* Create parent DMA tag. */
1720 error = bus_dma_tag_create(
1721 bus_get_dma_tag(sc->arge_dev), /* parent */
1722 1, 0, /* alignment, boundary */
1723 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1724 BUS_SPACE_MAXADDR, /* highaddr */
1725 NULL, NULL, /* filter, filterarg */
1726 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */

--- 43 unchanged lines hidden (view full) ---

1770 device_printf(sc->arge_dev,
1771 "failed to create Rx ring DMA tag\n");
1772 goto fail;
1773 }
1774
1775 /* Create tag for Tx buffers. */
1776 error = bus_dma_tag_create(
1777 sc->arge_cdata.arge_parent_tag, /* parent */
1780 /* Create parent DMA tag. */
1781 error = bus_dma_tag_create(
1782 bus_get_dma_tag(sc->arge_dev), /* parent */
1783 1, 0, /* alignment, boundary */
1784 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1785 BUS_SPACE_MAXADDR, /* highaddr */
1786 NULL, NULL, /* filter, filterarg */
1787 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */

--- 43 unchanged lines hidden (view full) ---

1831 device_printf(sc->arge_dev,
1832 "failed to create Rx ring DMA tag\n");
1833 goto fail;
1834 }
1835
1836 /* Create tag for Tx buffers. */
1837 error = bus_dma_tag_create(
1838 sc->arge_cdata.arge_parent_tag, /* parent */
1778 sizeof(uint32_t), 0, /* alignment, boundary */
1839 arge_tx_align, 0, /* alignment, boundary */
1779 BUS_SPACE_MAXADDR, /* lowaddr */
1780 BUS_SPACE_MAXADDR, /* highaddr */
1781 NULL, NULL, /* filter, filterarg */
1782 MCLBYTES * ARGE_MAXFRAGS, /* maxsize */
1783 ARGE_MAXFRAGS, /* nsegments */
1784 MCLBYTES, /* maxsegsize */
1785 0, /* flags */
1786 NULL, NULL, /* lockfunc, lockarg */
1787 &sc->arge_cdata.arge_tx_tag);
1788 if (error != 0) {
1789 device_printf(sc->arge_dev, "failed to create Tx DMA tag\n");
1790 goto fail;
1791 }
1792
1793 /* Create tag for Rx buffers. */
1794 error = bus_dma_tag_create(
1795 sc->arge_cdata.arge_parent_tag, /* parent */
1840 BUS_SPACE_MAXADDR, /* lowaddr */
1841 BUS_SPACE_MAXADDR, /* highaddr */
1842 NULL, NULL, /* filter, filterarg */
1843 MCLBYTES * ARGE_MAXFRAGS, /* maxsize */
1844 ARGE_MAXFRAGS, /* nsegments */
1845 MCLBYTES, /* maxsegsize */
1846 0, /* flags */
1847 NULL, NULL, /* lockfunc, lockarg */
1848 &sc->arge_cdata.arge_tx_tag);
1849 if (error != 0) {
1850 device_printf(sc->arge_dev, "failed to create Tx DMA tag\n");
1851 goto fail;
1852 }
1853
1854 /* Create tag for Rx buffers. */
1855 error = bus_dma_tag_create(
1856 sc->arge_cdata.arge_parent_tag, /* parent */
1796 ARGE_RX_ALIGN, 0, /* alignment, boundary */
1857 arge_rx_align, 0, /* alignment, boundary */
1797 BUS_SPACE_MAXADDR, /* lowaddr */
1798 BUS_SPACE_MAXADDR, /* highaddr */
1799 NULL, NULL, /* filter, filterarg */
1800 MCLBYTES, /* maxsize */
1801 ARGE_MAXFRAGS, /* nsegments */
1802 MCLBYTES, /* maxsegsize */
1803 0, /* flags */
1804 NULL, NULL, /* lockfunc, lockarg */

--- 298 unchanged lines hidden (view full) ---

2103 bus_dma_segment_t segs[1];
2104 bus_dmamap_t map;
2105 int nsegs;
2106
2107 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2108 if (m == NULL)
2109 return (ENOBUFS);
2110 m->m_len = m->m_pkthdr.len = MCLBYTES;
1858 BUS_SPACE_MAXADDR, /* lowaddr */
1859 BUS_SPACE_MAXADDR, /* highaddr */
1860 NULL, NULL, /* filter, filterarg */
1861 MCLBYTES, /* maxsize */
1862 ARGE_MAXFRAGS, /* nsegments */
1863 MCLBYTES, /* maxsegsize */
1864 0, /* flags */
1865 NULL, NULL, /* lockfunc, lockarg */

--- 298 unchanged lines hidden (view full) ---

2164 bus_dma_segment_t segs[1];
2165 bus_dmamap_t map;
2166 int nsegs;
2167
2168 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2169 if (m == NULL)
2170 return (ENOBUFS);
2171 m->m_len = m->m_pkthdr.len = MCLBYTES;
2172
2173 /*
2174 * Add extra space to "adjust" (copy) the packet back to be aligned
2175 * for purposes of IPv4/IPv6 header contents.
2176 */
2111 m_adj(m, sizeof(uint64_t));
2112
2113 if (bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_rx_tag,
2114 sc->arge_cdata.arge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
2115 m_freem(m);
2116 return (ENOBUFS);
2117 }
2118 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2119
2120 rxd = &sc->arge_cdata.arge_rxdesc[idx];
2121 if (rxd->rx_m != NULL) {
2122 bus_dmamap_unload(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap);
2123 }
2124 map = rxd->rx_dmamap;
2125 rxd->rx_dmamap = sc->arge_cdata.arge_rx_sparemap;
2126 sc->arge_cdata.arge_rx_sparemap = map;
2127 rxd->rx_m = m;
2128 desc = rxd->desc;
2177 m_adj(m, sizeof(uint64_t));
2178
2179 if (bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_rx_tag,
2180 sc->arge_cdata.arge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
2181 m_freem(m);
2182 return (ENOBUFS);
2183 }
2184 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2185
2186 rxd = &sc->arge_cdata.arge_rxdesc[idx];
2187 if (rxd->rx_m != NULL) {
2188 bus_dmamap_unload(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap);
2189 }
2190 map = rxd->rx_dmamap;
2191 rxd->rx_dmamap = sc->arge_cdata.arge_rx_sparemap;
2192 sc->arge_cdata.arge_rx_sparemap = map;
2193 rxd->rx_m = m;
2194 desc = rxd->desc;
2129 if (segs[0].ds_addr & 3)
2195 if ((sc->arge_hw_flags & ARGE_HW_FLG_RX_DESC_ALIGN_4BYTE) &&
2196 segs[0].ds_addr & 3)
2130 panic("RX packet address unaligned");
2131 desc->packet_addr = segs[0].ds_addr;
2132 desc->packet_ctrl = ARGE_DESC_EMPTY | ARGE_DMASIZE(segs[0].ds_len);
2133
2134 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2135 sc->arge_cdata.arge_rx_ring_map,
2136 BUS_DMASYNC_PREWRITE);
2137

--- 188 unchanged lines hidden (view full) ---

2326 "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2327 ARGEDEBUG(sc, ARGE_DBG_INTR, "status(filter) = %b\n", status,
2328 "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
2329 "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2330
2331 if (status & DMA_INTR_ALL) {
2332 sc->arge_intr_status |= status;
2333 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
2197 panic("RX packet address unaligned");
2198 desc->packet_addr = segs[0].ds_addr;
2199 desc->packet_ctrl = ARGE_DESC_EMPTY | ARGE_DMASIZE(segs[0].ds_len);
2200
2201 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
2202 sc->arge_cdata.arge_rx_ring_map,
2203 BUS_DMASYNC_PREWRITE);
2204

--- 188 unchanged lines hidden (view full) ---

2393 "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2394 ARGEDEBUG(sc, ARGE_DBG_INTR, "status(filter) = %b\n", status,
2395 "\20\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
2396 "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2397
2398 if (status & DMA_INTR_ALL) {
2399 sc->arge_intr_status |= status;
2400 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
2401 sc->stats.intr_ok++;
2334 return (FILTER_SCHEDULE_THREAD);
2335 }
2336
2337 sc->arge_intr_status = 0;
2402 return (FILTER_SCHEDULE_THREAD);
2403 }
2404
2405 sc->arge_intr_status = 0;
2406 sc->stats.intr_stray++;
2338 return (FILTER_STRAY);
2339}
2340
2341static void
2342arge_intr(void *arg)
2343{
2344 struct arge_softc *sc = arg;
2345 uint32_t status;

--- 4 unchanged lines hidden (view full) ---

2350
2351 ARGEDEBUG(sc, ARGE_DBG_INTR, "int status(intr) = %b\n", status,
2352 "\20\10\7RX_OVERFLOW\5RX_PKT_RCVD"
2353 "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2354
2355 /*
2356 * Is it our interrupt at all?
2357 */
2407 return (FILTER_STRAY);
2408}
2409
2410static void
2411arge_intr(void *arg)
2412{
2413 struct arge_softc *sc = arg;
2414 uint32_t status;

--- 4 unchanged lines hidden (view full) ---

2419
2420 ARGEDEBUG(sc, ARGE_DBG_INTR, "int status(intr) = %b\n", status,
2421 "\20\10\7RX_OVERFLOW\5RX_PKT_RCVD"
2422 "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
2423
2424 /*
2425 * Is it our interrupt at all?
2426 */
2358 if (status == 0)
2427 if (status == 0) {
2428 sc->stats.intr_stray2++;
2359 return;
2429 return;
2430 }
2360
2361 if (status & DMA_INTR_RX_BUS_ERROR) {
2362 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_BUS_ERROR);
2363 device_printf(sc->arge_dev, "RX bus error");
2364 return;
2365 }
2366
2367 if (status & DMA_INTR_TX_BUS_ERROR) {

--- 163 unchanged lines hidden --- 		2431
2432 if (status & DMA_INTR_RX_BUS_ERROR) {
2433 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_BUS_ERROR);
2434 device_printf(sc->arge_dev, "RX bus error");
2435 return;
2436 }
2437
2438 if (status & DMA_INTR_TX_BUS_ERROR) {

--- 163 unchanged lines hidden ---