| ar724xreg.h (261006) | ar724xreg.h (280313) |
|---|---|
| 1/*- 2 * Copyright (c) 2010 Adrian Chadd 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 10 unchanged lines hidden (view full) --- 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 | 1/*- 2 * Copyright (c) 2010 Adrian Chadd 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 10 unchanged lines hidden (view full) --- 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 |
| 27/* $FreeBSD: head/sys/mips/atheros/ar724xreg.h 261006 2014-01-22 08:02:07Z adrian $ */ | 27/* $FreeBSD: head/sys/mips/atheros/ar724xreg.h 280313 2015-03-21 05:59:45Z adrian $ */ |
| 28 29#ifndef __AR72XX_REG_H__ 30#define __AR72XX_REG_H__ 31 32#define AR724X_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00 33#define AR724X_PLL_REG_PCIE_CONFIG AR71XX_PLL_CPU_BASE + 0x18 34 35#define AR724X_PLL_DIV_SHIFT 0 --- 37 unchanged lines hidden (view full) --- 73#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000) 74#define AR724X_PCI_CRP_SIZE 0x100 75#define AR724X_PCI_CFG_BASE 0x14000000 76#define AR724X_PCI_CFG_SIZE 0x1000 77 78#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000) 79#define AR724X_PCI_CTRL_SIZE 0x100 80 | 28 29#ifndef __AR72XX_REG_H__ 30#define __AR72XX_REG_H__ 31 32#define AR724X_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00 33#define AR724X_PLL_REG_PCIE_CONFIG AR71XX_PLL_CPU_BASE + 0x18 34 35#define AR724X_PLL_DIV_SHIFT 0 --- 37 unchanged lines hidden (view full) --- 73#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000) 74#define AR724X_PCI_CRP_SIZE 0x100 75#define AR724X_PCI_CFG_BASE 0x14000000 76#define AR724X_PCI_CFG_SIZE 0x1000 77 78#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000) 79#define AR724X_PCI_CTRL_SIZE 0x100 80 |
| 81/* PCI config registers */ | 81/* PCI config registers - AR724X_PCI_CTRL_BASE */ |
| 82#define AR724X_PCI_APP 0x180f0000 83#define AR724X_PCI_APP_LTSSM_ENABLE (1 << 0) 84#define AR724X_PCI_RESET 0x180f0018 85#define AR724X_PCI_RESET_LINK_UP (1 << 0) 86#define AR724X_PCI_INTR_STATUS 0x180f004c 87#define AR724X_PCI_INTR_MASK 0x180f0050 88#define AR724X_PCI_INTR_DEV0 (1 << 14) 89 --- 19 unchanged lines hidden --- | 82#define AR724X_PCI_APP 0x180f0000 83#define AR724X_PCI_APP_LTSSM_ENABLE (1 << 0) 84#define AR724X_PCI_RESET 0x180f0018 85#define AR724X_PCI_RESET_LINK_UP (1 << 0) 86#define AR724X_PCI_INTR_STATUS 0x180f004c 87#define AR724X_PCI_INTR_MASK 0x180f0050 88#define AR724X_PCI_INTR_DEV0 (1 << 14) 89 --- 19 unchanged lines hidden --- |