| ar71xxreg.h (211476) | ar71xxreg.h (211502) |
|---|---|
| 1/*- 2 * Copyright (c) 2009 Oleksandr Tymoshenko 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 10 unchanged lines hidden (view full) --- 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 | 1/*- 2 * Copyright (c) 2009 Oleksandr Tymoshenko 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 10 unchanged lines hidden (view full) --- 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 |
| 27/* $FreeBSD: head/sys/mips/atheros/ar71xxreg.h 211476 2010-08-19 02:03:12Z adrian $ */ | 27/* $FreeBSD: head/sys/mips/atheros/ar71xxreg.h 211502 2010-08-19 11:40:10Z adrian $ */ |
| 28 29#ifndef _AR71XX_REG_H_ 30#define _AR71XX_REG_H_ 31 32/* PCI region */ 33#define AR71XX_PCI_MEM_BASE 0x10000000 34/* 35 * PCI mem windows is 0x08000000 bytes long but we exclude control --- 154 unchanged lines hidden (view full) --- 190#define XPLL_ETH_INT_CLK_1000 0x13110000 191#define XPLL_ETH_INT_CLK_1000_GMII 0x14110000 192#define PLL_ETH_INT_CLK_10 0x00991099 193#define PLL_ETH_INT_CLK_100 0x00001099 194#define PLL_ETH_INT_CLK_1000 0x00110000 195#define AR71XX_PLL_ETH_EXT_CLK 0x18050018 196#define AR71XX_PLL_PCI_CLK 0x1805001C 197 | 28 29#ifndef _AR71XX_REG_H_ 30#define _AR71XX_REG_H_ 31 32/* PCI region */ 33#define AR71XX_PCI_MEM_BASE 0x10000000 34/* 35 * PCI mem windows is 0x08000000 bytes long but we exclude control --- 154 unchanged lines hidden (view full) --- 190#define XPLL_ETH_INT_CLK_1000 0x13110000 191#define XPLL_ETH_INT_CLK_1000_GMII 0x14110000 192#define PLL_ETH_INT_CLK_10 0x00991099 193#define PLL_ETH_INT_CLK_100 0x00001099 194#define PLL_ETH_INT_CLK_1000 0x00110000 195#define AR71XX_PLL_ETH_EXT_CLK 0x18050018 196#define AR71XX_PLL_PCI_CLK 0x1805001C 197 |
| 198/* Reset block */ 199#define AR71XX_RST_BLOCK_BASE 0x18060000 200 |
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| 198#define AR71XX_RST_WDOG_CONTROL 0x18060008 199#define RST_WDOG_LAST (1 << 31) 200#define RST_WDOG_ACTION_MASK 3 201#define RST_WDOG_ACTION_RESET 3 202#define RST_WDOG_ACTION_NMI 2 203#define RST_WDOG_ACTION_GP_INTR 1 204#define RST_WDOG_ACTION_NOACTION 0 205 --- 42 unchanged lines hidden (view full) --- 248/* AR71XX chipset revision details */ 249#define AR71XX_REV_ID_MINOR_MASK 0x3 250#define AR71XX_REV_ID_MINOR_AR7130 0x0 251#define AR71XX_REV_ID_MINOR_AR7141 0x1 252#define AR71XX_REV_ID_MINOR_AR7161 0x2 253#define AR71XX_REV_ID_REVISION_MASK 0x3 254#define AR71XX_REV_ID_REVISION_SHIFT 2 255 | 201#define AR71XX_RST_WDOG_CONTROL 0x18060008 202#define RST_WDOG_LAST (1 << 31) 203#define RST_WDOG_ACTION_MASK 3 204#define RST_WDOG_ACTION_RESET 3 205#define RST_WDOG_ACTION_NMI 2 206#define RST_WDOG_ACTION_GP_INTR 1 207#define RST_WDOG_ACTION_NOACTION 0 208 --- 42 unchanged lines hidden (view full) --- 251/* AR71XX chipset revision details */ 252#define AR71XX_REV_ID_MINOR_MASK 0x3 253#define AR71XX_REV_ID_MINOR_AR7130 0x0 254#define AR71XX_REV_ID_MINOR_AR7141 0x1 255#define AR71XX_REV_ID_MINOR_AR7161 0x2 256#define AR71XX_REV_ID_REVISION_MASK 0x3 257#define AR71XX_REV_ID_REVISION_SHIFT 2 258 |
| 259/* AR91XX chipset revision details */ 260#define AR91XX_REV_ID_MINOR_MASK 0x3 261#define AR91XX_REV_ID_MINOR_AR9130 0x0 262#define AR91XX_REV_ID_MINOR_AR9132 0x1 263#define AR91XX_REV_ID_REVISION_MASK 0x3 264#define AR91XX_REV_ID_REVISION_SHIFT 2 265 |
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| 256/* 257 * GigE adapters region 258 */ 259#define AR71XX_MAC0_BASE 0x19000000 260#define AR71XX_MAC1_BASE 0x1A000000 261/* 262 * All 5 PHYs accessible only through MAC0 register space 263 */ --- 228 unchanged lines hidden --- | 266/* 267 * GigE adapters region 268 */ 269#define AR71XX_MAC0_BASE 0x19000000 270#define AR71XX_MAC1_BASE 0x1A000000 271/* 272 * All 5 PHYs accessible only through MAC0 register space 273 */ --- 228 unchanged lines hidden --- |