1/*-
2 * Copyright (c) 2010 Adrian Chadd
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2010 Adrian Chadd
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
|
28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_setup.c 276685 2015-01-05 02:06:26Z adrian $");
| 28__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_setup.c 290910 2015-11-16 04:28:00Z adrian $");
|
29
30#include "opt_ddb.h"
31
32#include <sys/param.h>
33#include <sys/conf.h>
34#include <sys/kernel.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/cons.h>
38#include <sys/kdb.h>
39#include <sys/reboot.h>
40
41#include <vm/vm.h>
42#include <vm/vm_page.h>
43
44#include <net/ethernet.h>
45
46#include <machine/clock.h>
47#include <machine/cpu.h>
48#include <machine/cpuregs.h>
49#include <machine/hwfunc.h>
50#include <machine/md_var.h>
51#include <machine/trap.h>
52#include <machine/vmparam.h>
53
54#include <mips/atheros/ar71xxreg.h>
55#include <mips/atheros/ar933xreg.h>
56#include <mips/atheros/ar934xreg.h>
57#include <mips/atheros/qca955xreg.h>
| 29
30#include "opt_ddb.h"
31
32#include <sys/param.h>
33#include <sys/conf.h>
34#include <sys/kernel.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/cons.h>
38#include <sys/kdb.h>
39#include <sys/reboot.h>
40
41#include <vm/vm.h>
42#include <vm/vm_page.h>
43
44#include <net/ethernet.h>
45
46#include <machine/clock.h>
47#include <machine/cpu.h>
48#include <machine/cpuregs.h>
49#include <machine/hwfunc.h>
50#include <machine/md_var.h>
51#include <machine/trap.h>
52#include <machine/vmparam.h>
53
54#include <mips/atheros/ar71xxreg.h>
55#include <mips/atheros/ar933xreg.h>
56#include <mips/atheros/ar934xreg.h>
57#include <mips/atheros/qca955xreg.h>
|
| 58#include <mips/atheros/qca953xreg.h>
|
58
59#include <mips/atheros/ar71xx_setup.h>
60
61#include <mips/atheros/ar71xx_cpudef.h>
62
63#include <mips/atheros/ar71xx_chip.h>
64#include <mips/atheros/ar724x_chip.h>
65#include <mips/atheros/ar91xx_chip.h>
66#include <mips/atheros/ar933x_chip.h>
67#include <mips/atheros/ar934x_chip.h>
| 59
60#include <mips/atheros/ar71xx_setup.h>
61
62#include <mips/atheros/ar71xx_cpudef.h>
63
64#include <mips/atheros/ar71xx_chip.h>
65#include <mips/atheros/ar724x_chip.h>
66#include <mips/atheros/ar91xx_chip.h>
67#include <mips/atheros/ar933x_chip.h>
68#include <mips/atheros/ar934x_chip.h>
|
| 69#include <mips/atheros/qca953x_chip.h>
|
68#include <mips/atheros/qca955x_chip.h>
69
70#define AR71XX_SYS_TYPE_LEN 128
71
72static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
73enum ar71xx_soc_type ar71xx_soc;
74struct ar71xx_cpu_def * ar71xx_cpu_ops = NULL;
75
76void
77ar71xx_detect_sys_type(void)
78{
79 char *chip = "????";
80 uint32_t id;
81 uint32_t major;
82 uint32_t minor;
83 uint32_t rev = 0;
84
85 id = ATH_READ_REG(AR71XX_RST_RESET_REG_REV_ID);
86 major = id & REV_ID_MAJOR_MASK;
87
88 switch (major) {
89 case REV_ID_MAJOR_AR71XX:
90 minor = id & AR71XX_REV_ID_MINOR_MASK;
91 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
92 rev &= AR71XX_REV_ID_REVISION_MASK;
93 ar71xx_cpu_ops = &ar71xx_chip_def;
94 switch (minor) {
95 case AR71XX_REV_ID_MINOR_AR7130:
96 ar71xx_soc = AR71XX_SOC_AR7130;
97 chip = "7130";
98 break;
99
100 case AR71XX_REV_ID_MINOR_AR7141:
101 ar71xx_soc = AR71XX_SOC_AR7141;
102 chip = "7141";
103 break;
104
105 case AR71XX_REV_ID_MINOR_AR7161:
106 ar71xx_soc = AR71XX_SOC_AR7161;
107 chip = "7161";
108 break;
109 }
110 break;
111
112 case REV_ID_MAJOR_AR7240:
113 ar71xx_soc = AR71XX_SOC_AR7240;
114 chip = "7240";
115 ar71xx_cpu_ops = &ar724x_chip_def;
116 rev = (id & AR724X_REV_ID_REVISION_MASK);
117 break;
118
119 case REV_ID_MAJOR_AR7241:
120 ar71xx_soc = AR71XX_SOC_AR7241;
121 chip = "7241";
122 ar71xx_cpu_ops = &ar724x_chip_def;
123 rev = (id & AR724X_REV_ID_REVISION_MASK);
124 break;
125
126 case REV_ID_MAJOR_AR7242:
127 ar71xx_soc = AR71XX_SOC_AR7242;
128 chip = "7242";
129 ar71xx_cpu_ops = &ar724x_chip_def;
130 rev = (id & AR724X_REV_ID_REVISION_MASK);
131 break;
132
133 case REV_ID_MAJOR_AR913X:
134 minor = id & AR91XX_REV_ID_MINOR_MASK;
135 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
136 rev &= AR91XX_REV_ID_REVISION_MASK;
137 ar71xx_cpu_ops = &ar91xx_chip_def;
138 switch (minor) {
139 case AR91XX_REV_ID_MINOR_AR9130:
140 ar71xx_soc = AR71XX_SOC_AR9130;
141 chip = "9130";
142 break;
143
144 case AR91XX_REV_ID_MINOR_AR9132:
145 ar71xx_soc = AR71XX_SOC_AR9132;
146 chip = "9132";
147 break;
148 }
149 break;
150 case REV_ID_MAJOR_AR9330:
151 minor = 0;
152 rev = (id & AR933X_REV_ID_REVISION_MASK);
153 chip = "9330";
154 ar71xx_cpu_ops = &ar933x_chip_def;
155 ar71xx_soc = AR71XX_SOC_AR9330;
156 break;
157 case REV_ID_MAJOR_AR9331:
158 minor = 1;
159 rev = (id & AR933X_REV_ID_REVISION_MASK);
160 chip = "9331";
161 ar71xx_soc = AR71XX_SOC_AR9331;
162 ar71xx_cpu_ops = &ar933x_chip_def;
163 break;
164
165 case REV_ID_MAJOR_AR9341:
166 minor = 0;
167 rev = (id & AR934X_REV_ID_REVISION_MASK);
168 chip = "9341";
169 ar71xx_soc = AR71XX_SOC_AR9341;
170 ar71xx_cpu_ops = &ar934x_chip_def;
171 break;
172
173 case REV_ID_MAJOR_AR9342:
174 minor = 0;
175 rev = (id & AR934X_REV_ID_REVISION_MASK);
176 chip = "9342";
177 ar71xx_soc = AR71XX_SOC_AR9342;
178 ar71xx_cpu_ops = &ar934x_chip_def;
179 break;
180
181 case REV_ID_MAJOR_AR9344:
182 minor = 0;
183 rev = (id & AR934X_REV_ID_REVISION_MASK);
184 chip = "9344";
185 ar71xx_soc = AR71XX_SOC_AR9344;
186 ar71xx_cpu_ops = &ar934x_chip_def;
187 break;
188
| 70#include <mips/atheros/qca955x_chip.h>
71
72#define AR71XX_SYS_TYPE_LEN 128
73
74static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
75enum ar71xx_soc_type ar71xx_soc;
76struct ar71xx_cpu_def * ar71xx_cpu_ops = NULL;
77
78void
79ar71xx_detect_sys_type(void)
80{
81 char *chip = "????";
82 uint32_t id;
83 uint32_t major;
84 uint32_t minor;
85 uint32_t rev = 0;
86
87 id = ATH_READ_REG(AR71XX_RST_RESET_REG_REV_ID);
88 major = id & REV_ID_MAJOR_MASK;
89
90 switch (major) {
91 case REV_ID_MAJOR_AR71XX:
92 minor = id & AR71XX_REV_ID_MINOR_MASK;
93 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
94 rev &= AR71XX_REV_ID_REVISION_MASK;
95 ar71xx_cpu_ops = &ar71xx_chip_def;
96 switch (minor) {
97 case AR71XX_REV_ID_MINOR_AR7130:
98 ar71xx_soc = AR71XX_SOC_AR7130;
99 chip = "7130";
100 break;
101
102 case AR71XX_REV_ID_MINOR_AR7141:
103 ar71xx_soc = AR71XX_SOC_AR7141;
104 chip = "7141";
105 break;
106
107 case AR71XX_REV_ID_MINOR_AR7161:
108 ar71xx_soc = AR71XX_SOC_AR7161;
109 chip = "7161";
110 break;
111 }
112 break;
113
114 case REV_ID_MAJOR_AR7240:
115 ar71xx_soc = AR71XX_SOC_AR7240;
116 chip = "7240";
117 ar71xx_cpu_ops = &ar724x_chip_def;
118 rev = (id & AR724X_REV_ID_REVISION_MASK);
119 break;
120
121 case REV_ID_MAJOR_AR7241:
122 ar71xx_soc = AR71XX_SOC_AR7241;
123 chip = "7241";
124 ar71xx_cpu_ops = &ar724x_chip_def;
125 rev = (id & AR724X_REV_ID_REVISION_MASK);
126 break;
127
128 case REV_ID_MAJOR_AR7242:
129 ar71xx_soc = AR71XX_SOC_AR7242;
130 chip = "7242";
131 ar71xx_cpu_ops = &ar724x_chip_def;
132 rev = (id & AR724X_REV_ID_REVISION_MASK);
133 break;
134
135 case REV_ID_MAJOR_AR913X:
136 minor = id & AR91XX_REV_ID_MINOR_MASK;
137 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
138 rev &= AR91XX_REV_ID_REVISION_MASK;
139 ar71xx_cpu_ops = &ar91xx_chip_def;
140 switch (minor) {
141 case AR91XX_REV_ID_MINOR_AR9130:
142 ar71xx_soc = AR71XX_SOC_AR9130;
143 chip = "9130";
144 break;
145
146 case AR91XX_REV_ID_MINOR_AR9132:
147 ar71xx_soc = AR71XX_SOC_AR9132;
148 chip = "9132";
149 break;
150 }
151 break;
152 case REV_ID_MAJOR_AR9330:
153 minor = 0;
154 rev = (id & AR933X_REV_ID_REVISION_MASK);
155 chip = "9330";
156 ar71xx_cpu_ops = &ar933x_chip_def;
157 ar71xx_soc = AR71XX_SOC_AR9330;
158 break;
159 case REV_ID_MAJOR_AR9331:
160 minor = 1;
161 rev = (id & AR933X_REV_ID_REVISION_MASK);
162 chip = "9331";
163 ar71xx_soc = AR71XX_SOC_AR9331;
164 ar71xx_cpu_ops = &ar933x_chip_def;
165 break;
166
167 case REV_ID_MAJOR_AR9341:
168 minor = 0;
169 rev = (id & AR934X_REV_ID_REVISION_MASK);
170 chip = "9341";
171 ar71xx_soc = AR71XX_SOC_AR9341;
172 ar71xx_cpu_ops = &ar934x_chip_def;
173 break;
174
175 case REV_ID_MAJOR_AR9342:
176 minor = 0;
177 rev = (id & AR934X_REV_ID_REVISION_MASK);
178 chip = "9342";
179 ar71xx_soc = AR71XX_SOC_AR9342;
180 ar71xx_cpu_ops = &ar934x_chip_def;
181 break;
182
183 case REV_ID_MAJOR_AR9344:
184 minor = 0;
185 rev = (id & AR934X_REV_ID_REVISION_MASK);
186 chip = "9344";
187 ar71xx_soc = AR71XX_SOC_AR9344;
188 ar71xx_cpu_ops = &ar934x_chip_def;
189 break;
190
|
| 191 case REV_ID_MAJOR_QCA9533:
192 minor = 0;
193 rev = (id & QCA953X_REV_ID_REVISION_MASK);
194 chip = "9533";
195 ar71xx_soc = AR71XX_SOC_QCA9533;
196 ar71xx_cpu_ops = &qca953x_chip_def;
197 break;
198
199 case REV_ID_MAJOR_QCA9533_V2:
200 minor = 0;
201 rev = (id & QCA953X_REV_ID_REVISION_MASK);
202 chip = "9533v2";
203 ar71xx_soc = AR71XX_SOC_QCA9533_V2;
204 ar71xx_cpu_ops = &qca953x_chip_def;
205 break;
206
|
189 case REV_ID_MAJOR_QCA9556:
190 minor = 0;
191 rev = (id & QCA955X_REV_ID_REVISION_MASK);
192 chip = "9556";
193 ar71xx_soc = AR71XX_SOC_QCA9556;
194 ar71xx_cpu_ops = &qca955x_chip_def;
195 break;
196
197 case REV_ID_MAJOR_QCA9558:
198 minor = 0;
199 rev = (id & QCA955X_REV_ID_REVISION_MASK);
200 chip = "9558";
201 ar71xx_soc = AR71XX_SOC_QCA9558;
202 ar71xx_cpu_ops = &qca955x_chip_def;
203 break;
204
205 default:
206 panic("ar71xx: unknown chip id:0x%08x\n", id);
207 }
208
209 sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
210}
211
212const char *
213ar71xx_get_system_type(void)
214{
215 return ar71xx_sys_type;
216}
217
| 207 case REV_ID_MAJOR_QCA9556:
208 minor = 0;
209 rev = (id & QCA955X_REV_ID_REVISION_MASK);
210 chip = "9556";
211 ar71xx_soc = AR71XX_SOC_QCA9556;
212 ar71xx_cpu_ops = &qca955x_chip_def;
213 break;
214
215 case REV_ID_MAJOR_QCA9558:
216 minor = 0;
217 rev = (id & QCA955X_REV_ID_REVISION_MASK);
218 chip = "9558";
219 ar71xx_soc = AR71XX_SOC_QCA9558;
220 ar71xx_cpu_ops = &qca955x_chip_def;
221 break;
222
223 default:
224 panic("ar71xx: unknown chip id:0x%08x\n", id);
225 }
226
227 sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
228}
229
230const char *
231ar71xx_get_system_type(void)
232{
233 return ar71xx_sys_type;
234}
235
|