1/*-
2 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
3 * Copyright (c) 2009, Luiz Otavio O Souza.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
11 * disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * GPIO driver for AR71xx
31 */
32
33#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
3 * Copyright (c) 2009, Luiz Otavio O Souza.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
11 * disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * GPIO driver for AR71xx
31 */
32
33#include <sys/cdefs.h>
|
34__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_gpio.c 277968 2015-01-31 12:17:07Z loos $");
| 34__FBSDID("$FreeBSD: head/sys/mips/atheros/ar71xx_gpio.c 277996 2015-01-31 19:32:14Z loos $");
|
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/bus.h>
39
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/rman.h>
43#include <sys/lock.h>
44#include <sys/malloc.h>
45#include <sys/mutex.h>
46#include <sys/gpio.h>
47
48#include <machine/bus.h>
49#include <machine/resource.h>
50#include <mips/atheros/ar71xxreg.h>
51#include <mips/atheros/ar71xx_setup.h>
52#include <mips/atheros/ar71xx_gpiovar.h>
53#include <mips/atheros/ar933xreg.h>
54#include <mips/atheros/ar934xreg.h>
| 35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/bus.h>
39
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/rman.h>
43#include <sys/lock.h>
44#include <sys/malloc.h>
45#include <sys/mutex.h>
46#include <sys/gpio.h>
47
48#include <machine/bus.h>
49#include <machine/resource.h>
50#include <mips/atheros/ar71xxreg.h>
51#include <mips/atheros/ar71xx_setup.h>
52#include <mips/atheros/ar71xx_gpiovar.h>
53#include <mips/atheros/ar933xreg.h>
54#include <mips/atheros/ar934xreg.h>
|
| 55#include <dev/gpio/gpiobusvar.h>
|
55
56#include "gpio_if.h"
57
58#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
59
60/*
61 * Helpers
62 */
63static void ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc,
64 uint32_t mask);
65static void ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc,
66 uint32_t mask);
67static void ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc,
68 struct gpio_pin *pin, uint32_t flags);
69
70/*
71 * Driver stuff
72 */
73static int ar71xx_gpio_probe(device_t dev);
74static int ar71xx_gpio_attach(device_t dev);
75static int ar71xx_gpio_detach(device_t dev);
76static int ar71xx_gpio_filter(void *arg);
77static void ar71xx_gpio_intr(void *arg);
78
79/*
80 * GPIO interface
81 */
| 56
57#include "gpio_if.h"
58
59#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
60
61/*
62 * Helpers
63 */
64static void ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc,
65 uint32_t mask);
66static void ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc,
67 uint32_t mask);
68static void ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc,
69 struct gpio_pin *pin, uint32_t flags);
70
71/*
72 * Driver stuff
73 */
74static int ar71xx_gpio_probe(device_t dev);
75static int ar71xx_gpio_attach(device_t dev);
76static int ar71xx_gpio_detach(device_t dev);
77static int ar71xx_gpio_filter(void *arg);
78static void ar71xx_gpio_intr(void *arg);
79
80/*
81 * GPIO interface
82 */
|
| 83static device_t ar71xx_gpio_get_bus(device_t);
|
82static int ar71xx_gpio_pin_max(device_t dev, int *maxpin);
83static int ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
84static int ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t
85 *flags);
86static int ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
87static int ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
88static int ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
89static int ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
90static int ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin);
91
92static void
93ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc, uint32_t mask)
94{
95 if (ar71xx_soc == AR71XX_SOC_AR9341 ||
96 ar71xx_soc == AR71XX_SOC_AR9342 ||
97 ar71xx_soc == AR71XX_SOC_AR9344)
98 GPIO_SET_BITS(sc, AR934X_GPIO_REG_FUNC, mask);
99 else
100 GPIO_SET_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
101}
102
103static void
104ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc, uint32_t mask)
105{
106 if (ar71xx_soc == AR71XX_SOC_AR9341 ||
107 ar71xx_soc == AR71XX_SOC_AR9342 ||
108 ar71xx_soc == AR71XX_SOC_AR9344)
109 GPIO_CLEAR_BITS(sc, AR934X_GPIO_REG_FUNC, mask);
110 else
111 GPIO_CLEAR_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
112}
113
114static void
115ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc, struct gpio_pin *pin,
116 unsigned int flags)
117{
118 uint32_t mask;
119
120 mask = 1 << pin->gp_pin;
121
122 /*
123 * Manage input/output
124 */
125 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
126 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
127 if (flags & GPIO_PIN_OUTPUT) {
128 pin->gp_flags |= GPIO_PIN_OUTPUT;
129 GPIO_SET_BITS(sc, AR71XX_GPIO_OE, mask);
130 }
131 else {
132 pin->gp_flags |= GPIO_PIN_INPUT;
133 GPIO_CLEAR_BITS(sc, AR71XX_GPIO_OE, mask);
134 }
135 }
136}
137
| 84static int ar71xx_gpio_pin_max(device_t dev, int *maxpin);
85static int ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
86static int ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t
87 *flags);
88static int ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
89static int ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
90static int ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
91static int ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
92static int ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin);
93
94static void
95ar71xx_gpio_function_enable(struct ar71xx_gpio_softc *sc, uint32_t mask)
96{
97 if (ar71xx_soc == AR71XX_SOC_AR9341 ||
98 ar71xx_soc == AR71XX_SOC_AR9342 ||
99 ar71xx_soc == AR71XX_SOC_AR9344)
100 GPIO_SET_BITS(sc, AR934X_GPIO_REG_FUNC, mask);
101 else
102 GPIO_SET_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
103}
104
105static void
106ar71xx_gpio_function_disable(struct ar71xx_gpio_softc *sc, uint32_t mask)
107{
108 if (ar71xx_soc == AR71XX_SOC_AR9341 ||
109 ar71xx_soc == AR71XX_SOC_AR9342 ||
110 ar71xx_soc == AR71XX_SOC_AR9344)
111 GPIO_CLEAR_BITS(sc, AR934X_GPIO_REG_FUNC, mask);
112 else
113 GPIO_CLEAR_BITS(sc, AR71XX_GPIO_FUNCTION, mask);
114}
115
116static void
117ar71xx_gpio_pin_configure(struct ar71xx_gpio_softc *sc, struct gpio_pin *pin,
118 unsigned int flags)
119{
120 uint32_t mask;
121
122 mask = 1 << pin->gp_pin;
123
124 /*
125 * Manage input/output
126 */
127 if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
128 pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
129 if (flags & GPIO_PIN_OUTPUT) {
130 pin->gp_flags |= GPIO_PIN_OUTPUT;
131 GPIO_SET_BITS(sc, AR71XX_GPIO_OE, mask);
132 }
133 else {
134 pin->gp_flags |= GPIO_PIN_INPUT;
135 GPIO_CLEAR_BITS(sc, AR71XX_GPIO_OE, mask);
136 }
137 }
138}
139
|
| 140static device_t
141ar71xx_gpio_get_bus(device_t dev)
142{
143 struct ar71xx_gpio_softc *sc;
144
145 sc = device_get_softc(dev);
146
147 return (sc->busdev);
148}
149
|
138static int
139ar71xx_gpio_pin_max(device_t dev, int *maxpin)
140{
141
142 switch (ar71xx_soc) {
143 case AR71XX_SOC_AR9130:
144 case AR71XX_SOC_AR9132:
145 *maxpin = AR91XX_GPIO_PINS - 1;
146 break;
147 case AR71XX_SOC_AR7240:
148 case AR71XX_SOC_AR7241:
149 case AR71XX_SOC_AR7242:
150 *maxpin = AR724X_GPIO_PINS - 1;
151 break;
152 case AR71XX_SOC_AR9330:
153 case AR71XX_SOC_AR9331:
154 *maxpin = AR933X_GPIO_COUNT - 1;
155 break;
156 case AR71XX_SOC_AR9341:
157 case AR71XX_SOC_AR9342:
158 case AR71XX_SOC_AR9344:
159 *maxpin = AR934X_GPIO_COUNT - 1;
160 break;
161 default:
162 *maxpin = AR71XX_GPIO_PINS - 1;
163 }
164 return (0);
165}
166
167static int
168ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
169{
170 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
171 int i;
172
173 for (i = 0; i < sc->gpio_npins; i++) {
174 if (sc->gpio_pins[i].gp_pin == pin)
175 break;
176 }
177
178 if (i >= sc->gpio_npins)
179 return (EINVAL);
180
181 GPIO_LOCK(sc);
182 *caps = sc->gpio_pins[i].gp_caps;
183 GPIO_UNLOCK(sc);
184
185 return (0);
186}
187
188static int
189ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
190{
191 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
192 int i;
193
194 for (i = 0; i < sc->gpio_npins; i++) {
195 if (sc->gpio_pins[i].gp_pin == pin)
196 break;
197 }
198
199 if (i >= sc->gpio_npins)
200 return (EINVAL);
201
202 GPIO_LOCK(sc);
203 *flags = sc->gpio_pins[i].gp_flags;
204 GPIO_UNLOCK(sc);
205
206 return (0);
207}
208
209static int
210ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
211{
212 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
213 int i;
214
215 for (i = 0; i < sc->gpio_npins; i++) {
216 if (sc->gpio_pins[i].gp_pin == pin)
217 break;
218 }
219
220 if (i >= sc->gpio_npins)
221 return (EINVAL);
222
223 GPIO_LOCK(sc);
224 memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
225 GPIO_UNLOCK(sc);
226
227 return (0);
228}
229
230static int
231ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
232{
233 int i;
234 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
235
236 for (i = 0; i < sc->gpio_npins; i++) {
237 if (sc->gpio_pins[i].gp_pin == pin)
238 break;
239 }
240
241 if (i >= sc->gpio_npins)
242 return (EINVAL);
243
244 ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);
245
246 return (0);
247}
248
249static int
250ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
251{
252 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
253 int i;
254
255 for (i = 0; i < sc->gpio_npins; i++) {
256 if (sc->gpio_pins[i].gp_pin == pin)
257 break;
258 }
259
260 if (i >= sc->gpio_npins)
261 return (EINVAL);
262
263 if (value)
264 GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
265 else
266 GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
267
268 return (0);
269}
270
271static int
272ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
273{
274 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
275 int i;
276
277 for (i = 0; i < sc->gpio_npins; i++) {
278 if (sc->gpio_pins[i].gp_pin == pin)
279 break;
280 }
281
282 if (i >= sc->gpio_npins)
283 return (EINVAL);
284
285 *val = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
286
287 return (0);
288}
289
290static int
291ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin)
292{
293 int res, i;
294 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
295
296 for (i = 0; i < sc->gpio_npins; i++) {
297 if (sc->gpio_pins[i].gp_pin == pin)
298 break;
299 }
300
301 if (i >= sc->gpio_npins)
302 return (EINVAL);
303
304 res = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
305 if (res)
306 GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
307 else
308 GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
309
310 return (0);
311}
312
313static int
314ar71xx_gpio_filter(void *arg)
315{
316
317 /* TODO: something useful */
318 return (FILTER_STRAY);
319}
320
321
322
323static void
324ar71xx_gpio_intr(void *arg)
325{
326 struct ar71xx_gpio_softc *sc = arg;
327 GPIO_LOCK(sc);
328 /* TODO: something useful */
329 GPIO_UNLOCK(sc);
330}
331
332static int
333ar71xx_gpio_probe(device_t dev)
334{
335
336 device_set_desc(dev, "Atheros AR71XX GPIO driver");
337 return (0);
338}
339
340static int
341ar71xx_gpio_attach(device_t dev)
342{
343 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
344 int i, j, maxpin;
345 int mask, pinon;
346 uint32_t oe;
347
348 KASSERT((device_get_unit(dev) == 0),
349 ("ar71xx_gpio: Only one gpio module supported"));
350
351 mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
352
353 /* Map control/status registers. */
354 sc->gpio_mem_rid = 0;
355 sc->gpio_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
356 &sc->gpio_mem_rid, RF_ACTIVE);
357
358 if (sc->gpio_mem_res == NULL) {
359 device_printf(dev, "couldn't map memory\n");
360 ar71xx_gpio_detach(dev);
361 return (ENXIO);
362 }
363
364 if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
365 &sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
366 device_printf(dev, "unable to allocate IRQ resource\n");
367 ar71xx_gpio_detach(dev);
368 return (ENXIO);
369 }
370
371 if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,
372 ar71xx_gpio_filter, ar71xx_gpio_intr, sc, &sc->gpio_ih))) {
373 device_printf(dev,
374 "WARNING: unable to register interrupt handler\n");
375 ar71xx_gpio_detach(dev);
376 return (ENXIO);
377 }
378
379 sc->dev = dev;
380
381 /* Enable function bits that are required */
382 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
383 "function_set", &mask) == 0) {
384 device_printf(dev, "function_set: 0x%x\n", mask);
385 ar71xx_gpio_function_enable(sc, mask);
386 }
387 /* Disable function bits that are required */
388 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
389 "function_clear", &mask) == 0) {
390 device_printf(dev, "function_clear: 0x%x\n", mask);
391 ar71xx_gpio_function_disable(sc, mask);
392 }
393
394 /* Disable interrupts for all pins. */
395 GPIO_WRITE(sc, AR71XX_GPIO_INT_MASK, 0);
396
397 /* Initialise all pins specified in the mask, up to the pin count */
398 (void) ar71xx_gpio_pin_max(dev, &maxpin);
399 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
400 "pinmask", &mask) != 0)
401 mask = 0;
402 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
403 "pinon", &pinon) != 0)
404 pinon = 0;
405 device_printf(dev, "gpio pinmask=0x%x\n", mask);
406 for (j = 0; j <= maxpin; j++) {
407 if ((mask & (1 << j)) == 0)
408 continue;
409 sc->gpio_npins++;
410 }
411 /* Iniatilize the GPIO pins, keep the loader settings. */
412 oe = GPIO_READ(sc, AR71XX_GPIO_OE);
413 sc->gpio_pins = malloc(sizeof(*sc->gpio_pins) * sc->gpio_npins,
414 M_DEVBUF, M_WAITOK | M_ZERO);
415 for (i = 0, j = 0; j <= maxpin; j++) {
416 if ((mask & (1 << j)) == 0)
417 continue;
418 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
419 "pin %d", j);
420 sc->gpio_pins[i].gp_pin = j;
421 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
422 if (oe & (1 << j))
423 sc->gpio_pins[i].gp_flags = GPIO_PIN_OUTPUT;
424 else
425 sc->gpio_pins[i].gp_flags = GPIO_PIN_INPUT;
426 i++;
427 }
428 /* Turn on the hinted pins. */
429 for (i = 0; i < sc->gpio_npins; i++) {
430 j = sc->gpio_pins[i].gp_pin;
431 if ((pinon & (1 << j)) != 0) {
432 ar71xx_gpio_pin_setflags(dev, j, GPIO_PIN_OUTPUT);
433 ar71xx_gpio_pin_set(dev, j, 1);
434 }
435 }
| 150static int
151ar71xx_gpio_pin_max(device_t dev, int *maxpin)
152{
153
154 switch (ar71xx_soc) {
155 case AR71XX_SOC_AR9130:
156 case AR71XX_SOC_AR9132:
157 *maxpin = AR91XX_GPIO_PINS - 1;
158 break;
159 case AR71XX_SOC_AR7240:
160 case AR71XX_SOC_AR7241:
161 case AR71XX_SOC_AR7242:
162 *maxpin = AR724X_GPIO_PINS - 1;
163 break;
164 case AR71XX_SOC_AR9330:
165 case AR71XX_SOC_AR9331:
166 *maxpin = AR933X_GPIO_COUNT - 1;
167 break;
168 case AR71XX_SOC_AR9341:
169 case AR71XX_SOC_AR9342:
170 case AR71XX_SOC_AR9344:
171 *maxpin = AR934X_GPIO_COUNT - 1;
172 break;
173 default:
174 *maxpin = AR71XX_GPIO_PINS - 1;
175 }
176 return (0);
177}
178
179static int
180ar71xx_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
181{
182 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
183 int i;
184
185 for (i = 0; i < sc->gpio_npins; i++) {
186 if (sc->gpio_pins[i].gp_pin == pin)
187 break;
188 }
189
190 if (i >= sc->gpio_npins)
191 return (EINVAL);
192
193 GPIO_LOCK(sc);
194 *caps = sc->gpio_pins[i].gp_caps;
195 GPIO_UNLOCK(sc);
196
197 return (0);
198}
199
200static int
201ar71xx_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
202{
203 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
204 int i;
205
206 for (i = 0; i < sc->gpio_npins; i++) {
207 if (sc->gpio_pins[i].gp_pin == pin)
208 break;
209 }
210
211 if (i >= sc->gpio_npins)
212 return (EINVAL);
213
214 GPIO_LOCK(sc);
215 *flags = sc->gpio_pins[i].gp_flags;
216 GPIO_UNLOCK(sc);
217
218 return (0);
219}
220
221static int
222ar71xx_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
223{
224 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
225 int i;
226
227 for (i = 0; i < sc->gpio_npins; i++) {
228 if (sc->gpio_pins[i].gp_pin == pin)
229 break;
230 }
231
232 if (i >= sc->gpio_npins)
233 return (EINVAL);
234
235 GPIO_LOCK(sc);
236 memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
237 GPIO_UNLOCK(sc);
238
239 return (0);
240}
241
242static int
243ar71xx_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
244{
245 int i;
246 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
247
248 for (i = 0; i < sc->gpio_npins; i++) {
249 if (sc->gpio_pins[i].gp_pin == pin)
250 break;
251 }
252
253 if (i >= sc->gpio_npins)
254 return (EINVAL);
255
256 ar71xx_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);
257
258 return (0);
259}
260
261static int
262ar71xx_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
263{
264 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
265 int i;
266
267 for (i = 0; i < sc->gpio_npins; i++) {
268 if (sc->gpio_pins[i].gp_pin == pin)
269 break;
270 }
271
272 if (i >= sc->gpio_npins)
273 return (EINVAL);
274
275 if (value)
276 GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
277 else
278 GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
279
280 return (0);
281}
282
283static int
284ar71xx_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
285{
286 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
287 int i;
288
289 for (i = 0; i < sc->gpio_npins; i++) {
290 if (sc->gpio_pins[i].gp_pin == pin)
291 break;
292 }
293
294 if (i >= sc->gpio_npins)
295 return (EINVAL);
296
297 *val = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
298
299 return (0);
300}
301
302static int
303ar71xx_gpio_pin_toggle(device_t dev, uint32_t pin)
304{
305 int res, i;
306 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
307
308 for (i = 0; i < sc->gpio_npins; i++) {
309 if (sc->gpio_pins[i].gp_pin == pin)
310 break;
311 }
312
313 if (i >= sc->gpio_npins)
314 return (EINVAL);
315
316 res = (GPIO_READ(sc, AR71XX_GPIO_IN) & (1 << pin)) ? 1 : 0;
317 if (res)
318 GPIO_WRITE(sc, AR71XX_GPIO_CLEAR, (1 << pin));
319 else
320 GPIO_WRITE(sc, AR71XX_GPIO_SET, (1 << pin));
321
322 return (0);
323}
324
325static int
326ar71xx_gpio_filter(void *arg)
327{
328
329 /* TODO: something useful */
330 return (FILTER_STRAY);
331}
332
333
334
335static void
336ar71xx_gpio_intr(void *arg)
337{
338 struct ar71xx_gpio_softc *sc = arg;
339 GPIO_LOCK(sc);
340 /* TODO: something useful */
341 GPIO_UNLOCK(sc);
342}
343
344static int
345ar71xx_gpio_probe(device_t dev)
346{
347
348 device_set_desc(dev, "Atheros AR71XX GPIO driver");
349 return (0);
350}
351
352static int
353ar71xx_gpio_attach(device_t dev)
354{
355 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
356 int i, j, maxpin;
357 int mask, pinon;
358 uint32_t oe;
359
360 KASSERT((device_get_unit(dev) == 0),
361 ("ar71xx_gpio: Only one gpio module supported"));
362
363 mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
364
365 /* Map control/status registers. */
366 sc->gpio_mem_rid = 0;
367 sc->gpio_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
368 &sc->gpio_mem_rid, RF_ACTIVE);
369
370 if (sc->gpio_mem_res == NULL) {
371 device_printf(dev, "couldn't map memory\n");
372 ar71xx_gpio_detach(dev);
373 return (ENXIO);
374 }
375
376 if ((sc->gpio_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
377 &sc->gpio_irq_rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
378 device_printf(dev, "unable to allocate IRQ resource\n");
379 ar71xx_gpio_detach(dev);
380 return (ENXIO);
381 }
382
383 if ((bus_setup_intr(dev, sc->gpio_irq_res, INTR_TYPE_MISC,
384 ar71xx_gpio_filter, ar71xx_gpio_intr, sc, &sc->gpio_ih))) {
385 device_printf(dev,
386 "WARNING: unable to register interrupt handler\n");
387 ar71xx_gpio_detach(dev);
388 return (ENXIO);
389 }
390
391 sc->dev = dev;
392
393 /* Enable function bits that are required */
394 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
395 "function_set", &mask) == 0) {
396 device_printf(dev, "function_set: 0x%x\n", mask);
397 ar71xx_gpio_function_enable(sc, mask);
398 }
399 /* Disable function bits that are required */
400 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
401 "function_clear", &mask) == 0) {
402 device_printf(dev, "function_clear: 0x%x\n", mask);
403 ar71xx_gpio_function_disable(sc, mask);
404 }
405
406 /* Disable interrupts for all pins. */
407 GPIO_WRITE(sc, AR71XX_GPIO_INT_MASK, 0);
408
409 /* Initialise all pins specified in the mask, up to the pin count */
410 (void) ar71xx_gpio_pin_max(dev, &maxpin);
411 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
412 "pinmask", &mask) != 0)
413 mask = 0;
414 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
415 "pinon", &pinon) != 0)
416 pinon = 0;
417 device_printf(dev, "gpio pinmask=0x%x\n", mask);
418 for (j = 0; j <= maxpin; j++) {
419 if ((mask & (1 << j)) == 0)
420 continue;
421 sc->gpio_npins++;
422 }
423 /* Iniatilize the GPIO pins, keep the loader settings. */
424 oe = GPIO_READ(sc, AR71XX_GPIO_OE);
425 sc->gpio_pins = malloc(sizeof(*sc->gpio_pins) * sc->gpio_npins,
426 M_DEVBUF, M_WAITOK | M_ZERO);
427 for (i = 0, j = 0; j <= maxpin; j++) {
428 if ((mask & (1 << j)) == 0)
429 continue;
430 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME,
431 "pin %d", j);
432 sc->gpio_pins[i].gp_pin = j;
433 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
434 if (oe & (1 << j))
435 sc->gpio_pins[i].gp_flags = GPIO_PIN_OUTPUT;
436 else
437 sc->gpio_pins[i].gp_flags = GPIO_PIN_INPUT;
438 i++;
439 }
440 /* Turn on the hinted pins. */
441 for (i = 0; i < sc->gpio_npins; i++) {
442 j = sc->gpio_pins[i].gp_pin;
443 if ((pinon & (1 << j)) != 0) {
444 ar71xx_gpio_pin_setflags(dev, j, GPIO_PIN_OUTPUT);
445 ar71xx_gpio_pin_set(dev, j, 1);
446 }
447 }
|
436 device_add_child(dev, "gpioc", -1);
437 device_add_child(dev, "gpiobus", -1);
| 448 sc->busdev = gpiobus_attach_bus(dev);
449 if (sc->busdev == NULL) {
450 ar71xx_gpio_detach(dev);
451 return (ENXIO);
452 }
|
438
| 453
|
439 return (bus_generic_attach(dev));
| 454 return (0);
|
440}
441
442static int
443ar71xx_gpio_detach(device_t dev)
444{
445 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
446
447 KASSERT(mtx_initialized(&sc->gpio_mtx), ("gpio mutex not initialized"));
448
| 455}
456
457static int
458ar71xx_gpio_detach(device_t dev)
459{
460 struct ar71xx_gpio_softc *sc = device_get_softc(dev);
461
462 KASSERT(mtx_initialized(&sc->gpio_mtx), ("gpio mutex not initialized"));
463
|
449 bus_generic_detach(dev);
| 464 gpiobus_detach_bus(dev);
|
450 if (sc->gpio_ih)
451 bus_teardown_intr(dev, sc->gpio_irq_res, sc->gpio_ih);
452 if (sc->gpio_irq_res)
453 bus_release_resource(dev, SYS_RES_IRQ, sc->gpio_irq_rid,
454 sc->gpio_irq_res);
455 if (sc->gpio_mem_res)
456 bus_release_resource(dev, SYS_RES_MEMORY, sc->gpio_mem_rid,
457 sc->gpio_mem_res);
458 if (sc->gpio_pins)
459 free(sc->gpio_pins, M_DEVBUF);
460 mtx_destroy(&sc->gpio_mtx);
461
462 return(0);
463}
464
465static device_method_t ar71xx_gpio_methods[] = {
466 DEVMETHOD(device_probe, ar71xx_gpio_probe),
467 DEVMETHOD(device_attach, ar71xx_gpio_attach),
468 DEVMETHOD(device_detach, ar71xx_gpio_detach),
469
470 /* GPIO protocol */
| 465 if (sc->gpio_ih)
466 bus_teardown_intr(dev, sc->gpio_irq_res, sc->gpio_ih);
467 if (sc->gpio_irq_res)
468 bus_release_resource(dev, SYS_RES_IRQ, sc->gpio_irq_rid,
469 sc->gpio_irq_res);
470 if (sc->gpio_mem_res)
471 bus_release_resource(dev, SYS_RES_MEMORY, sc->gpio_mem_rid,
472 sc->gpio_mem_res);
473 if (sc->gpio_pins)
474 free(sc->gpio_pins, M_DEVBUF);
475 mtx_destroy(&sc->gpio_mtx);
476
477 return(0);
478}
479
480static device_method_t ar71xx_gpio_methods[] = {
481 DEVMETHOD(device_probe, ar71xx_gpio_probe),
482 DEVMETHOD(device_attach, ar71xx_gpio_attach),
483 DEVMETHOD(device_detach, ar71xx_gpio_detach),
484
485 /* GPIO protocol */
|
| 486 DEVMETHOD(gpio_get_bus, ar71xx_gpio_get_bus),
|
471 DEVMETHOD(gpio_pin_max, ar71xx_gpio_pin_max),
472 DEVMETHOD(gpio_pin_getname, ar71xx_gpio_pin_getname),
473 DEVMETHOD(gpio_pin_getflags, ar71xx_gpio_pin_getflags),
474 DEVMETHOD(gpio_pin_getcaps, ar71xx_gpio_pin_getcaps),
475 DEVMETHOD(gpio_pin_setflags, ar71xx_gpio_pin_setflags),
476 DEVMETHOD(gpio_pin_get, ar71xx_gpio_pin_get),
477 DEVMETHOD(gpio_pin_set, ar71xx_gpio_pin_set),
478 DEVMETHOD(gpio_pin_toggle, ar71xx_gpio_pin_toggle),
479 {0, 0},
480};
481
482static driver_t ar71xx_gpio_driver = {
483 "gpio",
484 ar71xx_gpio_methods,
485 sizeof(struct ar71xx_gpio_softc),
486};
487static devclass_t ar71xx_gpio_devclass;
488
489DRIVER_MODULE(ar71xx_gpio, apb, ar71xx_gpio_driver, ar71xx_gpio_devclass, 0, 0);
| 487 DEVMETHOD(gpio_pin_max, ar71xx_gpio_pin_max),
488 DEVMETHOD(gpio_pin_getname, ar71xx_gpio_pin_getname),
489 DEVMETHOD(gpio_pin_getflags, ar71xx_gpio_pin_getflags),
490 DEVMETHOD(gpio_pin_getcaps, ar71xx_gpio_pin_getcaps),
491 DEVMETHOD(gpio_pin_setflags, ar71xx_gpio_pin_setflags),
492 DEVMETHOD(gpio_pin_get, ar71xx_gpio_pin_get),
493 DEVMETHOD(gpio_pin_set, ar71xx_gpio_pin_set),
494 DEVMETHOD(gpio_pin_toggle, ar71xx_gpio_pin_toggle),
495 {0, 0},
496};
497
498static driver_t ar71xx_gpio_driver = {
499 "gpio",
500 ar71xx_gpio_methods,
501 sizeof(struct ar71xx_gpio_softc),
502};
503static devclass_t ar71xx_gpio_devclass;
504
505DRIVER_MODULE(ar71xx_gpio, apb, ar71xx_gpio_driver, ar71xx_gpio_devclass, 0, 0);
|