| pci_cfgreg.c (267992) | pci_cfgreg.c (282274) |
|---|---|
| 1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * Copyright (c) 2004, Scott Long <scottl@freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 14 unchanged lines hidden (view full) --- 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * Copyright (c) 2004, Scott Long <scottl@freebsd.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 14 unchanged lines hidden (view full) --- 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> |
| 31__FBSDID("$FreeBSD: head/sys/i386/pci/pci_cfgreg.c 267992 2014-06-28 03:56:17Z hselasky $"); | 31__FBSDID("$FreeBSD: head/sys/i386/pci/pci_cfgreg.c 282274 2015-04-30 15:48:48Z jhb $"); |
| 32 33#include "opt_xbox.h" 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/lock.h> 39#include <sys/kernel.h> --- 48 unchanged lines hidden (view full) --- 88static int mcfg_enable = 1; 89SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0, 90 "Enable support for PCI-e memory mapped config access"); 91 92static uint32_t pci_docfgregread(int bus, int slot, int func, int reg, 93 int bytes); 94static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes); 95static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes); | 32 33#include "opt_xbox.h" 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/lock.h> 39#include <sys/kernel.h> --- 48 unchanged lines hidden (view full) --- 88static int mcfg_enable = 1; 89SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0, 90 "Enable support for PCI-e memory mapped config access"); 91 92static uint32_t pci_docfgregread(int bus, int slot, int func, int reg, 93 int bytes); 94static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes); 95static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes); |
| 96#ifndef XEN | |
| 97static int pcireg_cfgopen(void); | 96static int pcireg_cfgopen(void); |
| 98#endif | |
| 99static int pciereg_cfgread(int bus, unsigned slot, unsigned func, 100 unsigned reg, unsigned bytes); 101static void pciereg_cfgwrite(int bus, unsigned slot, unsigned func, 102 unsigned reg, int data, unsigned bytes); 103 104/* 105 * Some BIOS writers seem to want to ignore the spec and put 106 * 0 in the intline rather than 255 to indicate none. Some use --- 4 unchanged lines hidden (view full) --- 111static __inline int 112pci_i386_map_intline(int line) 113{ 114 if (line == 0 || line >= 128) 115 return (PCI_INVALID_IRQ); 116 return (line); 117} 118 | 97static int pciereg_cfgread(int bus, unsigned slot, unsigned func, 98 unsigned reg, unsigned bytes); 99static void pciereg_cfgwrite(int bus, unsigned slot, unsigned func, 100 unsigned reg, int data, unsigned bytes); 101 102/* 103 * Some BIOS writers seem to want to ignore the spec and put 104 * 0 in the intline rather than 255 to indicate none. Some use --- 4 unchanged lines hidden (view full) --- 109static __inline int 110pci_i386_map_intline(int line) 111{ 112 if (line == 0 || line >= 128) 113 return (PCI_INVALID_IRQ); 114 return (line); 115} 116 |
| 119#ifndef XEN | |
| 120static u_int16_t 121pcibios_get_version(void) 122{ 123 struct bios_regs args; 124 125 if (PCIbios.ventry == 0) { 126 PRVERB(("pcibios: No call entry point\n")); 127 return (0); --- 4 unchanged lines hidden (view full) --- 132 return (0); 133 } 134 if (args.edx != 0x20494350) { 135 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n")); 136 return (0); 137 } 138 return (args.ebx & 0xffff); 139} | 117static u_int16_t 118pcibios_get_version(void) 119{ 120 struct bios_regs args; 121 122 if (PCIbios.ventry == 0) { 123 PRVERB(("pcibios: No call entry point\n")); 124 return (0); --- 4 unchanged lines hidden (view full) --- 129 return (0); 130 } 131 if (args.edx != 0x20494350) { 132 PRVERB(("pcibios: BIOS_PRESENT didn't return 'PCI ' in edx\n")); 133 return (0); 134 } 135 return (args.ebx & 0xffff); 136} |
| 140#endif | |
| 141 142/* 143 * Initialise access to PCI configuration space 144 */ 145int 146pci_cfgregopen(void) 147{ | 137 138/* 139 * Initialise access to PCI configuration space 140 */ 141int 142pci_cfgregopen(void) 143{ |
| 148#ifdef XEN 149 return (0); 150#else | |
| 151 static int opened = 0; 152 uint64_t pciebar; 153 u_int16_t vid, did; 154 u_int16_t v; 155 156 if (opened) 157 return (1); 158 --- 38 unchanged lines hidden (view full) --- 197 /* Intel 915, 925, or 915GM */ 198 pciebar = pci_cfgregread(0, 0, 0, 0x48, 4); 199 pcie_cfgregopen(pciebar, 0, 255); 200 break; 201 } 202 } 203 204 return(1); | 144 static int opened = 0; 145 uint64_t pciebar; 146 u_int16_t vid, did; 147 u_int16_t v; 148 149 if (opened) 150 return (1); 151 --- 38 unchanged lines hidden (view full) --- 190 /* Intel 915, 925, or 915GM */ 191 pciebar = pci_cfgregread(0, 0, 0, 0x48, 4); 192 pcie_cfgregopen(pciebar, 0, 255); 193 break; 194 } 195 } 196 197 return(1); |
| 205#endif | |
| 206} 207 208static uint32_t 209pci_docfgregread(int bus, int slot, int func, int reg, int bytes) 210{ 211 212 if (cfgmech == CFGMECH_PCIE && 213 (bus >= pcie_minbus && bus <= pcie_maxbus) && --- 171 unchanged lines hidden (view full) --- 385 outl(port, data); 386 break; 387 } 388 pci_cfgdisable(); 389 } 390 mtx_unlock_spin(&pcicfg_mtx); 391} 392 | 198} 199 200static uint32_t 201pci_docfgregread(int bus, int slot, int func, int reg, int bytes) 202{ 203 204 if (cfgmech == CFGMECH_PCIE && 205 (bus >= pcie_minbus && bus <= pcie_maxbus) && --- 171 unchanged lines hidden (view full) --- 377 outl(port, data); 378 break; 379 } 380 pci_cfgdisable(); 381 } 382 mtx_unlock_spin(&pcicfg_mtx); 383} 384 |
| 393#ifndef XEN | |
| 394/* check whether the configuration mechanism has been correctly identified */ 395static int 396pci_cfgcheck(int maxdev) 397{ 398 uint32_t id, class; 399 uint8_t header; 400 uint8_t device; 401 int port; --- 200 unchanged lines hidden (view full) --- 602 val2 = pciereg_cfgread(0, slot, 0, 0, 4); 603 if (val2 != val1) 604 pcie_badslots |= (1 << slot); 605 } 606 } 607 608 return (1); 609} | 385/* check whether the configuration mechanism has been correctly identified */ 386static int 387pci_cfgcheck(int maxdev) 388{ 389 uint32_t id, class; 390 uint8_t header; 391 uint8_t device; 392 int port; --- 200 unchanged lines hidden (view full) --- 593 val2 = pciereg_cfgread(0, slot, 0, 0, 4); 594 if (val2 != val1) 595 pcie_badslots |= (1 << slot); 596 } 597 } 598 599 return (1); 600} |
| 610#endif /* !XEN */ | |
| 611 612#define PCIE_PADDR(base, reg, bus, slot, func) \ 613 ((base) + \ 614 ((((bus) & 0xff) << 20) | \ 615 (((slot) & 0x1f) << 15) | \ 616 (((func) & 0x7) << 12) | \ 617 ((reg) & 0xfff))) 618 --- 110 unchanged lines hidden --- | 601 602#define PCIE_PADDR(base, reg, bus, slot, func) \ 603 ((base) + \ 604 ((((bus) & 0xff) << 20) | \ 605 (((slot) & 0x1f) << 15) | \ 606 (((func) & 0x7) << 12) | \ 607 ((reg) & 0xfff))) 608 --- 110 unchanged lines hidden --- |