263 return (result); 264 265#endif /* SMP */ 266} 267 268static int 269npx_probe1(dev) 270 device_t dev; 271{ 272#ifndef SMP 273 u_short control; 274 u_short status; 275#endif 276 277 /* 278 * Partially reset the coprocessor, if any. Some BIOS's don't reset 279 * it after a warm boot. 280 */ 281 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 282 outb(0xf0, 0); /* clear BUSY# latch */ 283 /* 284 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 285 * instructions. We must set the CR0_MP bit and use the CR0_TS 286 * bit to control the trap, because setting the CR0_EM bit does 287 * not cause WAIT instructions to trap. It's important to trap 288 * WAIT instructions - otherwise the "wait" variants of no-wait 289 * control instructions would degenerate to the "no-wait" variants 290 * after FP context switches but work correctly otherwise. It's 291 * particularly important to trap WAITs when there is no NPX - 292 * otherwise the "wait" variants would always degenerate. 293 * 294 * Try setting CR0_NE to get correct error reporting on 486DX's. 295 * Setting it should fail or do nothing on lesser processors. 296 */ 297 load_cr0(rcr0() | CR0_MP | CR0_NE); 298 /* 299 * But don't trap while we're probing. 300 */ 301 stop_emulating(); 302 /* 303 * Finish resetting the coprocessor, if any. If there is an error 304 * pending, then we may get a bogus IRQ13, but probeintr() will handle 305 * it OK. Bogus halts have never been observed, but we enabled 306 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 307 */ 308 fninit(); 309 310#ifdef SMP 311 /* 312 * Exception 16 MUST work for SMP. 313 */ 314 npx_irq13 = 0; 315 npx_ex16 = hw_float = npx_exists = 1; 316 device_set_desc(dev, "math processor"); 317 return (0); 318 319#else /* !SMP */ 320 device_set_desc(dev, "math processor"); 321 322 /* 323 * Don't use fwait here because it might hang. 324 * Don't use fnop here because it usually hangs if there is no FPU. 325 */ 326 DELAY(1000); /* wait for any IRQ13 */ 327#ifdef DIAGNOSTIC 328 if (npx_intrs_while_probing != 0) 329 printf("fninit caused %u bogus npx interrupt(s)\n", 330 npx_intrs_while_probing); 331 if (npx_traps_while_probing != 0) 332 printf("fninit caused %u bogus npx trap(s)\n", 333 npx_traps_while_probing); 334#endif 335 /* 336 * Check for a status of mostly zero. 337 */ 338 status = 0x5a5a; 339 fnstsw(&status); 340 if ((status & 0xb8ff) == 0) { 341 /* 342 * Good, now check for a proper control word. 343 */ 344 control = 0x5a5a; 345 fnstcw(&control); 346 if ((control & 0x1f3f) == 0x033f) { 347 hw_float = npx_exists = 1; 348 /* 349 * We have an npx, now divide by 0 to see if exception 350 * 16 works. 351 */ 352 control &= ~(1 << 2); /* enable divide by 0 trap */ 353 fldcw(&control); 354 npx_traps_while_probing = npx_intrs_while_probing = 0; 355 fp_divide_by_0(); 356 if (npx_traps_while_probing != 0) { 357 /* 358 * Good, exception 16 works. 359 */ 360 npx_ex16 = 1; 361 return (0); 362 } 363 if (npx_intrs_while_probing != 0) { 364 int rid; 365 struct resource *r; 366 void *intr; 367 /* 368 * Bad, we are stuck with IRQ13. 369 */ 370 npx_irq13 = 1; 371 /* 372 * npxattach would be too late to set npx0_imask 373 */ 374 npx0_imask |= (1 << npx_irq); 375 376 /* 377 * We allocate these resources permanently, 378 * so there is no need to keep track of them. 379 */ 380 rid = 0; 381 r = bus_alloc_resource(dev, SYS_RES_IOPORT, 382 &rid, IO_NPX, IO_NPX, 383 IO_NPXSIZE, RF_ACTIVE); 384 if (r == 0) 385 panic("npx: can't get ports"); 386 rid = 0; 387 r = bus_alloc_resource(dev, SYS_RES_IRQ, 388 &rid, npx_irq, npx_irq, 389 1, RF_ACTIVE); 390 if (r == 0) 391 panic("npx: can't get IRQ"); 392 BUS_SETUP_INTR(device_get_parent(dev), 393 dev, r, 394 INTR_TYPE_MISC | INTR_MPSAFE, 395 npx_intr, 0, &intr); 396 if (intr == 0) 397 panic("npx: can't create intr"); 398 399 return (0); 400 } 401 /* 402 * Worse, even IRQ13 is broken. Use emulator. 403 */ 404 } 405 } 406 /* 407 * Probe failed, but we want to get to npxattach to initialize the 408 * emulator and say that it has been installed. XXX handle devices 409 * that aren't really devices better. 410 */ 411 return (0); 412#endif /* SMP */ 413} 414 415/* 416 * Attach routine - announce which it is, and wire into system 417 */ 418int 419npx_attach(dev) 420 device_t dev; 421{ 422 int flags; 423 424 if (resource_int_value("npx", 0, "flags", &flags) != 0) 425 flags = 0; 426 427 if (flags) 428 device_printf(dev, "flags 0x%x ", flags); 429 if (npx_irq13) { 430 device_printf(dev, "using IRQ 13 interface\n"); 431 } else { 432#if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) 433 if (npx_ex16) { 434 if (!(flags & NPX_PREFER_EMULATOR)) 435 device_printf(dev, "INT 16 interface\n"); 436 else { 437 device_printf(dev, "FPU exists, but flags request " 438 "emulator\n"); 439 hw_float = npx_exists = 0; 440 } 441 } else if (npx_exists) { 442 device_printf(dev, "error reporting broken; using 387 emulator\n"); 443 hw_float = npx_exists = 0; 444 } else 445 device_printf(dev, "387 emulator\n"); 446#else 447 if (npx_ex16) { 448 device_printf(dev, "INT 16 interface\n"); 449 if (flags & NPX_PREFER_EMULATOR) { 450 device_printf(dev, "emulator requested, but none compiled " 451 "into kernel, using FPU\n"); 452 } 453 } else 454 device_printf(dev, "no 387 emulator in kernel and no FPU!\n"); 455#endif 456 } 457 npxinit(__INITIAL_NPXCW__); 458 459#ifdef I586_CPU 460 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 461 timezero("i586_bzero()", i586_bzero) < 462 timezero("bzero()", bzero) * 4 / 5) { 463 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) { 464 bcopy_vector = i586_bcopy; 465 ovbcopy_vector = i586_bcopy; 466 } 467 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 468 bzero = i586_bzero; 469 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 470 copyin_vector = i586_copyin; 471 copyout_vector = i586_copyout; 472 } 473 } 474#endif 475 476 return (0); /* XXX unused */ 477} 478 479/* 480 * Initialize floating point unit. 481 */ 482void 483npxinit(control) 484 u_short control; 485{ 486 struct save87 dummy; 487 488 if (!npx_exists) 489 return; 490 /* 491 * fninit has the same h/w bugs as fnsave. Use the detoxified 492 * fnsave to throw away any junk in the fpu. npxsave() initializes 493 * the fpu and sets npxproc = NULL as important side effects. 494 */ 495 npxsave(&dummy); 496 stop_emulating(); 497 fldcw(&control); 498 if (PCPU_GET(curpcb) != NULL) 499 fnsave(&PCPU_GET(curpcb)->pcb_savefpu); 500 start_emulating(); 501} 502 503/* 504 * Free coprocessor (if we have it). 505 */ 506void 507npxexit(p) 508 struct proc *p; 509{ 510 511 if (p == PCPU_GET(npxproc)) 512 npxsave(&PCPU_GET(curpcb)->pcb_savefpu); 513#ifdef NPX_DEBUG 514 if (npx_exists) { 515 u_int masked_exceptions; 516 517 masked_exceptions = PCPU_GET(curpcb)->pcb_savefpu.sv_env.en_cw 518 & PCPU_GET(curpcb)->pcb_savefpu.sv_env.en_sw & 0x7f; 519 /* 520 * Log exceptions that would have trapped with the old 521 * control word (overflow, divide by 0, and invalid operand). 522 */ 523 if (masked_exceptions & 0x0d) 524 log(LOG_ERR, 525 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 526 p->p_pid, p->p_comm, masked_exceptions); 527 } 528#endif 529} 530 531/* 532 * The following mechanism is used to ensure that the FPE_... value 533 * that is passed as a trapcode to the signal handler of the user 534 * process does not have more than one bit set. 535 * 536 * Multiple bits may be set if the user process modifies the control 537 * word while a status word bit is already set. While this is a sign 538 * of bad coding, we have no choise than to narrow them down to one 539 * bit, since we must not send a trapcode that is not exactly one of 540 * the FPE_ macros. 541 * 542 * The mechanism has a static table with 127 entries. Each combination 543 * of the 7 FPU status word exception bits directly translates to a 544 * position in this table, where a single FPE_... value is stored. 545 * This FPE_... value stored there is considered the "most important" 546 * of the exception bits and will be sent as the signal code. The 547 * precedence of the bits is based upon Intel Document "Numerical 548 * Applications", Chapter "Special Computational Situations". 549 * 550 * The macro to choose one of these values does these steps: 1) Throw 551 * away status word bits that cannot be masked. 2) Throw away the bits 552 * currently masked in the control word, assuming the user isn't 553 * interested in them anymore. 3) Reinsert status word bit 7 (stack 554 * fault) if it is set, which cannot be masked but must be presered. 555 * 4) Use the remaining bits to point into the trapcode table. 556 * 557 * The 6 maskable bits in order of their preference, as stated in the 558 * above referenced Intel manual: 559 * 1 Invalid operation (FP_X_INV) 560 * 1a Stack underflow 561 * 1b Stack overflow 562 * 1c Operand of unsupported format 563 * 1d SNaN operand. 564 * 2 QNaN operand (not an exception, irrelavant here) 565 * 3 Any other invalid-operation not mentioned above or zero divide 566 * (FP_X_INV, FP_X_DZ) 567 * 4 Denormal operand (FP_X_DNML) 568 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 569 * 6 Inexact result (FP_X_IMP) 570 */ 571static char fpetable[128] = { 572 0, 573 FPE_FLTINV, /* 1 - INV */ 574 FPE_FLTUND, /* 2 - DNML */ 575 FPE_FLTINV, /* 3 - INV | DNML */ 576 FPE_FLTDIV, /* 4 - DZ */ 577 FPE_FLTINV, /* 5 - INV | DZ */ 578 FPE_FLTDIV, /* 6 - DNML | DZ */ 579 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 580 FPE_FLTOVF, /* 8 - OFL */ 581 FPE_FLTINV, /* 9 - INV | OFL */ 582 FPE_FLTUND, /* A - DNML | OFL */ 583 FPE_FLTINV, /* B - INV | DNML | OFL */ 584 FPE_FLTDIV, /* C - DZ | OFL */ 585 FPE_FLTINV, /* D - INV | DZ | OFL */ 586 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 587 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 588 FPE_FLTUND, /* 10 - UFL */ 589 FPE_FLTINV, /* 11 - INV | UFL */ 590 FPE_FLTUND, /* 12 - DNML | UFL */ 591 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 592 FPE_FLTDIV, /* 14 - DZ | UFL */ 593 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 594 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 595 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 596 FPE_FLTOVF, /* 18 - OFL | UFL */ 597 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 598 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 599 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 600 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 601 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 602 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 603 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 604 FPE_FLTRES, /* 20 - IMP */ 605 FPE_FLTINV, /* 21 - INV | IMP */ 606 FPE_FLTUND, /* 22 - DNML | IMP */ 607 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 608 FPE_FLTDIV, /* 24 - DZ | IMP */ 609 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 610 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 611 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 612 FPE_FLTOVF, /* 28 - OFL | IMP */ 613 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 614 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 615 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 616 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 617 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 618 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 619 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 620 FPE_FLTUND, /* 30 - UFL | IMP */ 621 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 622 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 623 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 624 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 625 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 626 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 627 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 628 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 629 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 630 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 631 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 632 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 633 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 634 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 635 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 636 FPE_FLTSUB, /* 40 - STK */ 637 FPE_FLTSUB, /* 41 - INV | STK */ 638 FPE_FLTUND, /* 42 - DNML | STK */ 639 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 640 FPE_FLTDIV, /* 44 - DZ | STK */ 641 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 642 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 643 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 644 FPE_FLTOVF, /* 48 - OFL | STK */ 645 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 646 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 647 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 648 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 649 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 650 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 651 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 652 FPE_FLTUND, /* 50 - UFL | STK */ 653 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 654 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 655 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 656 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 657 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 658 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 659 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 660 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 661 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 662 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 663 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 664 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 665 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 666 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 667 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 668 FPE_FLTRES, /* 60 - IMP | STK */ 669 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 670 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 671 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 672 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 673 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 674 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 675 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 676 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 677 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 678 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 679 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 680 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 681 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 682 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 683 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 684 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 685 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 686 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 687 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 688 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 689 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 690 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 691 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 692 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 693 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 694 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 695 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 696 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 697 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 698 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 699 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 700}; 701 702/* 703 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 704 * 705 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 706 * depend on longjmp() restoring a usable state. Restoring the state 707 * or examining it might fail if we didn't clear exceptions. 708 * 709 * The error code chosen will be one of the FPE_... macros. It will be 710 * sent as the second argument to old BSD-style signal handlers and as 711 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 712 * 713 * XXX the FP state is not preserved across signal handlers. So signal 714 * handlers cannot afford to do FP unless they preserve the state or 715 * longjmp() out. Both preserving the state and longjmp()ing may be 716 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 717 * solution for signals other than SIGFPE. 718 */ 719void 720npx_intr(dummy) 721 void *dummy; 722{ 723 int code; 724 u_short control; 725 struct intrframe *frame; 726 727 mtx_lock(&Giant); 728 if (PCPU_GET(npxproc) == NULL || !npx_exists) { 729 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 730 PCPU_GET(npxproc), curproc, npx_exists); 731 panic("npxintr from nowhere"); 732 } 733 if (PCPU_GET(npxproc) != curproc) { 734 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 735 PCPU_GET(npxproc), curproc, npx_exists); 736 panic("npxintr from non-current process"); 737 } 738 739 outb(0xf0, 0); 740 fnstsw(&PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw); 741 fnstcw(&control); 742 fnclex(); 743 744 /* 745 * Pass exception to process. 746 */ 747 frame = (struct intrframe *)&dummy; /* XXX */ 748 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) { 749 /* 750 * Interrupt is essentially a trap, so we can afford to call 751 * the SIGFPE handler (if any) as soon as the interrupt 752 * returns. 753 * 754 * XXX little or nothing is gained from this, and plenty is 755 * lost - the interrupt frame has to contain the trap frame 756 * (this is otherwise only necessary for the rescheduling trap 757 * in doreti, and the frame for that could easily be set up 758 * just before it is used). 759 */ 760 curproc->p_md.md_regs = INTR_TO_TRAPFRAME(frame); 761 /* 762 * Encode the appropriate code for detailed information on 763 * this exception. 764 */ 765 code = 766 fpetable[(PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw & ~control & 0x3f) | 767 (PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw & 0x40)]; 768 trapsignal(curproc, SIGFPE, code); 769 } else { 770 /* 771 * Nested interrupt. These losers occur when: 772 * o an IRQ13 is bogusly generated at a bogus time, e.g.: 773 * o immediately after an fnsave or frstor of an 774 * error state. 775 * o a couple of 386 instructions after 776 * "fstpl _memvar" causes a stack overflow. 777 * These are especially nasty when combined with a 778 * trace trap. 779 * o an IRQ13 occurs at the same time as another higher- 780 * priority interrupt. 781 * 782 * Treat them like a true async interrupt. 783 */ 784 PROC_LOCK(curproc); 785 psignal(curproc, SIGFPE); 786 PROC_UNLOCK(curproc); 787 } 788 mtx_unlock(&Giant); 789} 790 791/* 792 * Implement device not available (DNA) exception 793 * 794 * It would be better to switch FP context here (if curproc != npxproc) 795 * and not necessarily for every context switch, but it is too hard to 796 * access foreign pcb's. 797 */ 798int 799npxdna() 800{
| 262 return (result); 263 264#endif /* SMP */ 265} 266 267static int 268npx_probe1(dev) 269 device_t dev; 270{ 271#ifndef SMP 272 u_short control; 273 u_short status; 274#endif 275 276 /* 277 * Partially reset the coprocessor, if any. Some BIOS's don't reset 278 * it after a warm boot. 279 */ 280 outb(0xf1, 0); /* full reset on some systems, NOP on others */ 281 outb(0xf0, 0); /* clear BUSY# latch */ 282 /* 283 * Prepare to trap all ESC (i.e., NPX) instructions and all WAIT 284 * instructions. We must set the CR0_MP bit and use the CR0_TS 285 * bit to control the trap, because setting the CR0_EM bit does 286 * not cause WAIT instructions to trap. It's important to trap 287 * WAIT instructions - otherwise the "wait" variants of no-wait 288 * control instructions would degenerate to the "no-wait" variants 289 * after FP context switches but work correctly otherwise. It's 290 * particularly important to trap WAITs when there is no NPX - 291 * otherwise the "wait" variants would always degenerate. 292 * 293 * Try setting CR0_NE to get correct error reporting on 486DX's. 294 * Setting it should fail or do nothing on lesser processors. 295 */ 296 load_cr0(rcr0() | CR0_MP | CR0_NE); 297 /* 298 * But don't trap while we're probing. 299 */ 300 stop_emulating(); 301 /* 302 * Finish resetting the coprocessor, if any. If there is an error 303 * pending, then we may get a bogus IRQ13, but probeintr() will handle 304 * it OK. Bogus halts have never been observed, but we enabled 305 * IRQ13 and cleared the BUSY# latch early to handle them anyway. 306 */ 307 fninit(); 308 309#ifdef SMP 310 /* 311 * Exception 16 MUST work for SMP. 312 */ 313 npx_irq13 = 0; 314 npx_ex16 = hw_float = npx_exists = 1; 315 device_set_desc(dev, "math processor"); 316 return (0); 317 318#else /* !SMP */ 319 device_set_desc(dev, "math processor"); 320 321 /* 322 * Don't use fwait here because it might hang. 323 * Don't use fnop here because it usually hangs if there is no FPU. 324 */ 325 DELAY(1000); /* wait for any IRQ13 */ 326#ifdef DIAGNOSTIC 327 if (npx_intrs_while_probing != 0) 328 printf("fninit caused %u bogus npx interrupt(s)\n", 329 npx_intrs_while_probing); 330 if (npx_traps_while_probing != 0) 331 printf("fninit caused %u bogus npx trap(s)\n", 332 npx_traps_while_probing); 333#endif 334 /* 335 * Check for a status of mostly zero. 336 */ 337 status = 0x5a5a; 338 fnstsw(&status); 339 if ((status & 0xb8ff) == 0) { 340 /* 341 * Good, now check for a proper control word. 342 */ 343 control = 0x5a5a; 344 fnstcw(&control); 345 if ((control & 0x1f3f) == 0x033f) { 346 hw_float = npx_exists = 1; 347 /* 348 * We have an npx, now divide by 0 to see if exception 349 * 16 works. 350 */ 351 control &= ~(1 << 2); /* enable divide by 0 trap */ 352 fldcw(&control); 353 npx_traps_while_probing = npx_intrs_while_probing = 0; 354 fp_divide_by_0(); 355 if (npx_traps_while_probing != 0) { 356 /* 357 * Good, exception 16 works. 358 */ 359 npx_ex16 = 1; 360 return (0); 361 } 362 if (npx_intrs_while_probing != 0) { 363 int rid; 364 struct resource *r; 365 void *intr; 366 /* 367 * Bad, we are stuck with IRQ13. 368 */ 369 npx_irq13 = 1; 370 /* 371 * npxattach would be too late to set npx0_imask 372 */ 373 npx0_imask |= (1 << npx_irq); 374 375 /* 376 * We allocate these resources permanently, 377 * so there is no need to keep track of them. 378 */ 379 rid = 0; 380 r = bus_alloc_resource(dev, SYS_RES_IOPORT, 381 &rid, IO_NPX, IO_NPX, 382 IO_NPXSIZE, RF_ACTIVE); 383 if (r == 0) 384 panic("npx: can't get ports"); 385 rid = 0; 386 r = bus_alloc_resource(dev, SYS_RES_IRQ, 387 &rid, npx_irq, npx_irq, 388 1, RF_ACTIVE); 389 if (r == 0) 390 panic("npx: can't get IRQ"); 391 BUS_SETUP_INTR(device_get_parent(dev), 392 dev, r, 393 INTR_TYPE_MISC | INTR_MPSAFE, 394 npx_intr, 0, &intr); 395 if (intr == 0) 396 panic("npx: can't create intr"); 397 398 return (0); 399 } 400 /* 401 * Worse, even IRQ13 is broken. Use emulator. 402 */ 403 } 404 } 405 /* 406 * Probe failed, but we want to get to npxattach to initialize the 407 * emulator and say that it has been installed. XXX handle devices 408 * that aren't really devices better. 409 */ 410 return (0); 411#endif /* SMP */ 412} 413 414/* 415 * Attach routine - announce which it is, and wire into system 416 */ 417int 418npx_attach(dev) 419 device_t dev; 420{ 421 int flags; 422 423 if (resource_int_value("npx", 0, "flags", &flags) != 0) 424 flags = 0; 425 426 if (flags) 427 device_printf(dev, "flags 0x%x ", flags); 428 if (npx_irq13) { 429 device_printf(dev, "using IRQ 13 interface\n"); 430 } else { 431#if defined(MATH_EMULATE) || defined(GPL_MATH_EMULATE) 432 if (npx_ex16) { 433 if (!(flags & NPX_PREFER_EMULATOR)) 434 device_printf(dev, "INT 16 interface\n"); 435 else { 436 device_printf(dev, "FPU exists, but flags request " 437 "emulator\n"); 438 hw_float = npx_exists = 0; 439 } 440 } else if (npx_exists) { 441 device_printf(dev, "error reporting broken; using 387 emulator\n"); 442 hw_float = npx_exists = 0; 443 } else 444 device_printf(dev, "387 emulator\n"); 445#else 446 if (npx_ex16) { 447 device_printf(dev, "INT 16 interface\n"); 448 if (flags & NPX_PREFER_EMULATOR) { 449 device_printf(dev, "emulator requested, but none compiled " 450 "into kernel, using FPU\n"); 451 } 452 } else 453 device_printf(dev, "no 387 emulator in kernel and no FPU!\n"); 454#endif 455 } 456 npxinit(__INITIAL_NPXCW__); 457 458#ifdef I586_CPU 459 if (cpu_class == CPUCLASS_586 && npx_ex16 && npx_exists && 460 timezero("i586_bzero()", i586_bzero) < 461 timezero("bzero()", bzero) * 4 / 5) { 462 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BCOPY)) { 463 bcopy_vector = i586_bcopy; 464 ovbcopy_vector = i586_bcopy; 465 } 466 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_BZERO)) 467 bzero = i586_bzero; 468 if (!(flags & NPX_DISABLE_I586_OPTIMIZED_COPYIO)) { 469 copyin_vector = i586_copyin; 470 copyout_vector = i586_copyout; 471 } 472 } 473#endif 474 475 return (0); /* XXX unused */ 476} 477 478/* 479 * Initialize floating point unit. 480 */ 481void 482npxinit(control) 483 u_short control; 484{ 485 struct save87 dummy; 486 487 if (!npx_exists) 488 return; 489 /* 490 * fninit has the same h/w bugs as fnsave. Use the detoxified 491 * fnsave to throw away any junk in the fpu. npxsave() initializes 492 * the fpu and sets npxproc = NULL as important side effects. 493 */ 494 npxsave(&dummy); 495 stop_emulating(); 496 fldcw(&control); 497 if (PCPU_GET(curpcb) != NULL) 498 fnsave(&PCPU_GET(curpcb)->pcb_savefpu); 499 start_emulating(); 500} 501 502/* 503 * Free coprocessor (if we have it). 504 */ 505void 506npxexit(p) 507 struct proc *p; 508{ 509 510 if (p == PCPU_GET(npxproc)) 511 npxsave(&PCPU_GET(curpcb)->pcb_savefpu); 512#ifdef NPX_DEBUG 513 if (npx_exists) { 514 u_int masked_exceptions; 515 516 masked_exceptions = PCPU_GET(curpcb)->pcb_savefpu.sv_env.en_cw 517 & PCPU_GET(curpcb)->pcb_savefpu.sv_env.en_sw & 0x7f; 518 /* 519 * Log exceptions that would have trapped with the old 520 * control word (overflow, divide by 0, and invalid operand). 521 */ 522 if (masked_exceptions & 0x0d) 523 log(LOG_ERR, 524 "pid %d (%s) exited with masked floating point exceptions 0x%02x\n", 525 p->p_pid, p->p_comm, masked_exceptions); 526 } 527#endif 528} 529 530/* 531 * The following mechanism is used to ensure that the FPE_... value 532 * that is passed as a trapcode to the signal handler of the user 533 * process does not have more than one bit set. 534 * 535 * Multiple bits may be set if the user process modifies the control 536 * word while a status word bit is already set. While this is a sign 537 * of bad coding, we have no choise than to narrow them down to one 538 * bit, since we must not send a trapcode that is not exactly one of 539 * the FPE_ macros. 540 * 541 * The mechanism has a static table with 127 entries. Each combination 542 * of the 7 FPU status word exception bits directly translates to a 543 * position in this table, where a single FPE_... value is stored. 544 * This FPE_... value stored there is considered the "most important" 545 * of the exception bits and will be sent as the signal code. The 546 * precedence of the bits is based upon Intel Document "Numerical 547 * Applications", Chapter "Special Computational Situations". 548 * 549 * The macro to choose one of these values does these steps: 1) Throw 550 * away status word bits that cannot be masked. 2) Throw away the bits 551 * currently masked in the control word, assuming the user isn't 552 * interested in them anymore. 3) Reinsert status word bit 7 (stack 553 * fault) if it is set, which cannot be masked but must be presered. 554 * 4) Use the remaining bits to point into the trapcode table. 555 * 556 * The 6 maskable bits in order of their preference, as stated in the 557 * above referenced Intel manual: 558 * 1 Invalid operation (FP_X_INV) 559 * 1a Stack underflow 560 * 1b Stack overflow 561 * 1c Operand of unsupported format 562 * 1d SNaN operand. 563 * 2 QNaN operand (not an exception, irrelavant here) 564 * 3 Any other invalid-operation not mentioned above or zero divide 565 * (FP_X_INV, FP_X_DZ) 566 * 4 Denormal operand (FP_X_DNML) 567 * 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL) 568 * 6 Inexact result (FP_X_IMP) 569 */ 570static char fpetable[128] = { 571 0, 572 FPE_FLTINV, /* 1 - INV */ 573 FPE_FLTUND, /* 2 - DNML */ 574 FPE_FLTINV, /* 3 - INV | DNML */ 575 FPE_FLTDIV, /* 4 - DZ */ 576 FPE_FLTINV, /* 5 - INV | DZ */ 577 FPE_FLTDIV, /* 6 - DNML | DZ */ 578 FPE_FLTINV, /* 7 - INV | DNML | DZ */ 579 FPE_FLTOVF, /* 8 - OFL */ 580 FPE_FLTINV, /* 9 - INV | OFL */ 581 FPE_FLTUND, /* A - DNML | OFL */ 582 FPE_FLTINV, /* B - INV | DNML | OFL */ 583 FPE_FLTDIV, /* C - DZ | OFL */ 584 FPE_FLTINV, /* D - INV | DZ | OFL */ 585 FPE_FLTDIV, /* E - DNML | DZ | OFL */ 586 FPE_FLTINV, /* F - INV | DNML | DZ | OFL */ 587 FPE_FLTUND, /* 10 - UFL */ 588 FPE_FLTINV, /* 11 - INV | UFL */ 589 FPE_FLTUND, /* 12 - DNML | UFL */ 590 FPE_FLTINV, /* 13 - INV | DNML | UFL */ 591 FPE_FLTDIV, /* 14 - DZ | UFL */ 592 FPE_FLTINV, /* 15 - INV | DZ | UFL */ 593 FPE_FLTDIV, /* 16 - DNML | DZ | UFL */ 594 FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */ 595 FPE_FLTOVF, /* 18 - OFL | UFL */ 596 FPE_FLTINV, /* 19 - INV | OFL | UFL */ 597 FPE_FLTUND, /* 1A - DNML | OFL | UFL */ 598 FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */ 599 FPE_FLTDIV, /* 1C - DZ | OFL | UFL */ 600 FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */ 601 FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */ 602 FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */ 603 FPE_FLTRES, /* 20 - IMP */ 604 FPE_FLTINV, /* 21 - INV | IMP */ 605 FPE_FLTUND, /* 22 - DNML | IMP */ 606 FPE_FLTINV, /* 23 - INV | DNML | IMP */ 607 FPE_FLTDIV, /* 24 - DZ | IMP */ 608 FPE_FLTINV, /* 25 - INV | DZ | IMP */ 609 FPE_FLTDIV, /* 26 - DNML | DZ | IMP */ 610 FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */ 611 FPE_FLTOVF, /* 28 - OFL | IMP */ 612 FPE_FLTINV, /* 29 - INV | OFL | IMP */ 613 FPE_FLTUND, /* 2A - DNML | OFL | IMP */ 614 FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */ 615 FPE_FLTDIV, /* 2C - DZ | OFL | IMP */ 616 FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */ 617 FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */ 618 FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */ 619 FPE_FLTUND, /* 30 - UFL | IMP */ 620 FPE_FLTINV, /* 31 - INV | UFL | IMP */ 621 FPE_FLTUND, /* 32 - DNML | UFL | IMP */ 622 FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */ 623 FPE_FLTDIV, /* 34 - DZ | UFL | IMP */ 624 FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */ 625 FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */ 626 FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */ 627 FPE_FLTOVF, /* 38 - OFL | UFL | IMP */ 628 FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */ 629 FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */ 630 FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */ 631 FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */ 632 FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */ 633 FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */ 634 FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */ 635 FPE_FLTSUB, /* 40 - STK */ 636 FPE_FLTSUB, /* 41 - INV | STK */ 637 FPE_FLTUND, /* 42 - DNML | STK */ 638 FPE_FLTSUB, /* 43 - INV | DNML | STK */ 639 FPE_FLTDIV, /* 44 - DZ | STK */ 640 FPE_FLTSUB, /* 45 - INV | DZ | STK */ 641 FPE_FLTDIV, /* 46 - DNML | DZ | STK */ 642 FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */ 643 FPE_FLTOVF, /* 48 - OFL | STK */ 644 FPE_FLTSUB, /* 49 - INV | OFL | STK */ 645 FPE_FLTUND, /* 4A - DNML | OFL | STK */ 646 FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */ 647 FPE_FLTDIV, /* 4C - DZ | OFL | STK */ 648 FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */ 649 FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */ 650 FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */ 651 FPE_FLTUND, /* 50 - UFL | STK */ 652 FPE_FLTSUB, /* 51 - INV | UFL | STK */ 653 FPE_FLTUND, /* 52 - DNML | UFL | STK */ 654 FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */ 655 FPE_FLTDIV, /* 54 - DZ | UFL | STK */ 656 FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */ 657 FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */ 658 FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */ 659 FPE_FLTOVF, /* 58 - OFL | UFL | STK */ 660 FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */ 661 FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */ 662 FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */ 663 FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */ 664 FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */ 665 FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */ 666 FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */ 667 FPE_FLTRES, /* 60 - IMP | STK */ 668 FPE_FLTSUB, /* 61 - INV | IMP | STK */ 669 FPE_FLTUND, /* 62 - DNML | IMP | STK */ 670 FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */ 671 FPE_FLTDIV, /* 64 - DZ | IMP | STK */ 672 FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */ 673 FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */ 674 FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */ 675 FPE_FLTOVF, /* 68 - OFL | IMP | STK */ 676 FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */ 677 FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */ 678 FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */ 679 FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */ 680 FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */ 681 FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */ 682 FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */ 683 FPE_FLTUND, /* 70 - UFL | IMP | STK */ 684 FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */ 685 FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */ 686 FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */ 687 FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */ 688 FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */ 689 FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */ 690 FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */ 691 FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */ 692 FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */ 693 FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */ 694 FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */ 695 FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */ 696 FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */ 697 FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */ 698 FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */ 699}; 700 701/* 702 * Preserve the FP status word, clear FP exceptions, then generate a SIGFPE. 703 * 704 * Clearing exceptions is necessary mainly to avoid IRQ13 bugs. We now 705 * depend on longjmp() restoring a usable state. Restoring the state 706 * or examining it might fail if we didn't clear exceptions. 707 * 708 * The error code chosen will be one of the FPE_... macros. It will be 709 * sent as the second argument to old BSD-style signal handlers and as 710 * "siginfo_t->si_code" (second argument) to SA_SIGINFO signal handlers. 711 * 712 * XXX the FP state is not preserved across signal handlers. So signal 713 * handlers cannot afford to do FP unless they preserve the state or 714 * longjmp() out. Both preserving the state and longjmp()ing may be 715 * destroyed by IRQ13 bugs. Clearing FP exceptions is not an acceptable 716 * solution for signals other than SIGFPE. 717 */ 718void 719npx_intr(dummy) 720 void *dummy; 721{ 722 int code; 723 u_short control; 724 struct intrframe *frame; 725 726 mtx_lock(&Giant); 727 if (PCPU_GET(npxproc) == NULL || !npx_exists) { 728 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 729 PCPU_GET(npxproc), curproc, npx_exists); 730 panic("npxintr from nowhere"); 731 } 732 if (PCPU_GET(npxproc) != curproc) { 733 printf("npxintr: npxproc = %p, curproc = %p, npx_exists = %d\n", 734 PCPU_GET(npxproc), curproc, npx_exists); 735 panic("npxintr from non-current process"); 736 } 737 738 outb(0xf0, 0); 739 fnstsw(&PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw); 740 fnstcw(&control); 741 fnclex(); 742 743 /* 744 * Pass exception to process. 745 */ 746 frame = (struct intrframe *)&dummy; /* XXX */ 747 if ((ISPL(frame->if_cs) == SEL_UPL) || (frame->if_eflags & PSL_VM)) { 748 /* 749 * Interrupt is essentially a trap, so we can afford to call 750 * the SIGFPE handler (if any) as soon as the interrupt 751 * returns. 752 * 753 * XXX little or nothing is gained from this, and plenty is 754 * lost - the interrupt frame has to contain the trap frame 755 * (this is otherwise only necessary for the rescheduling trap 756 * in doreti, and the frame for that could easily be set up 757 * just before it is used). 758 */ 759 curproc->p_md.md_regs = INTR_TO_TRAPFRAME(frame); 760 /* 761 * Encode the appropriate code for detailed information on 762 * this exception. 763 */ 764 code = 765 fpetable[(PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw & ~control & 0x3f) | 766 (PCPU_GET(curpcb)->pcb_savefpu.sv_ex_sw & 0x40)]; 767 trapsignal(curproc, SIGFPE, code); 768 } else { 769 /* 770 * Nested interrupt. These losers occur when: 771 * o an IRQ13 is bogusly generated at a bogus time, e.g.: 772 * o immediately after an fnsave or frstor of an 773 * error state. 774 * o a couple of 386 instructions after 775 * "fstpl _memvar" causes a stack overflow. 776 * These are especially nasty when combined with a 777 * trace trap. 778 * o an IRQ13 occurs at the same time as another higher- 779 * priority interrupt. 780 * 781 * Treat them like a true async interrupt. 782 */ 783 PROC_LOCK(curproc); 784 psignal(curproc, SIGFPE); 785 PROC_UNLOCK(curproc); 786 } 787 mtx_unlock(&Giant); 788} 789 790/* 791 * Implement device not available (DNA) exception 792 * 793 * It would be better to switch FP context here (if curproc != npxproc) 794 * and not necessarily for every context switch, but it is too hard to 795 * access foreign pcb's. 796 */ 797int 798npxdna() 799{
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889 890#endif /* SMP */ 891} 892 893#ifdef I586_CPU 894static long 895timezero(funcname, func) 896 const char *funcname; 897 void (*func) __P((void *buf, size_t len)); 898 899{ 900 void *buf; 901#define BUFSIZE 1048576 902 long usec; 903 struct timeval finish, start; 904 905 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 906 if (buf == NULL) 907 return (BUFSIZE); 908 microtime(&start); 909 (*func)(buf, BUFSIZE); 910 microtime(&finish); 911 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 912 finish.tv_usec - start.tv_usec; 913 if (usec <= 0) 914 usec = 1; 915 if (bootverbose) 916 printf("%s bandwidth = %lu kBps\n", funcname, 917 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 918 free(buf, M_TEMP); 919 return (usec); 920} 921#endif /* I586_CPU */ 922 923static device_method_t npx_methods[] = { 924 /* Device interface */ 925 DEVMETHOD(device_identify, npx_identify), 926 DEVMETHOD(device_probe, npx_probe), 927 DEVMETHOD(device_attach, npx_attach), 928 DEVMETHOD(device_detach, bus_generic_detach), 929 DEVMETHOD(device_shutdown, bus_generic_shutdown), 930 DEVMETHOD(device_suspend, bus_generic_suspend), 931 DEVMETHOD(device_resume, bus_generic_resume), 932 933 { 0, 0 } 934}; 935 936static driver_t npx_driver = { 937 "npx", 938 npx_methods, 939 1, /* no softc */ 940}; 941 942static devclass_t npx_devclass; 943 944/* 945 * We prefer to attach to the root nexus so that the usual case (exception 16) 946 * doesn't describe the processor as being `on isa'. 947 */ 948DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 949 950/* 951 * This sucks up the legacy ISA support assignments from PNPBIOS. 952 */ 953static struct isa_pnp_id npxisa_ids[] = { 954 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 955 { 0 } 956}; 957 958static int 959npxisa_probe(device_t dev) 960{ 961 int result; 962 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 963 device_quiet(dev); 964 } 965 return(result); 966} 967 968static int 969npxisa_attach(device_t dev) 970{ 971 return (0); 972} 973 974static device_method_t npxisa_methods[] = { 975 /* Device interface */ 976 DEVMETHOD(device_probe, npxisa_probe), 977 DEVMETHOD(device_attach, npxisa_attach), 978 DEVMETHOD(device_detach, bus_generic_detach), 979 DEVMETHOD(device_shutdown, bus_generic_shutdown), 980 DEVMETHOD(device_suspend, bus_generic_suspend), 981 DEVMETHOD(device_resume, bus_generic_resume), 982 983 { 0, 0 } 984}; 985 986static driver_t npxisa_driver = { 987 "npxisa", 988 npxisa_methods, 989 1, /* no softc */ 990}; 991 992static devclass_t npxisa_devclass; 993 994DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 995
| 886 887#endif /* SMP */ 888} 889 890#ifdef I586_CPU 891static long 892timezero(funcname, func) 893 const char *funcname; 894 void (*func) __P((void *buf, size_t len)); 895 896{ 897 void *buf; 898#define BUFSIZE 1048576 899 long usec; 900 struct timeval finish, start; 901 902 buf = malloc(BUFSIZE, M_TEMP, M_NOWAIT); 903 if (buf == NULL) 904 return (BUFSIZE); 905 microtime(&start); 906 (*func)(buf, BUFSIZE); 907 microtime(&finish); 908 usec = 1000000 * (finish.tv_sec - start.tv_sec) + 909 finish.tv_usec - start.tv_usec; 910 if (usec <= 0) 911 usec = 1; 912 if (bootverbose) 913 printf("%s bandwidth = %lu kBps\n", funcname, 914 (u_int32_t)(((BUFSIZE >> 10) * 1000000) / usec)); 915 free(buf, M_TEMP); 916 return (usec); 917} 918#endif /* I586_CPU */ 919 920static device_method_t npx_methods[] = { 921 /* Device interface */ 922 DEVMETHOD(device_identify, npx_identify), 923 DEVMETHOD(device_probe, npx_probe), 924 DEVMETHOD(device_attach, npx_attach), 925 DEVMETHOD(device_detach, bus_generic_detach), 926 DEVMETHOD(device_shutdown, bus_generic_shutdown), 927 DEVMETHOD(device_suspend, bus_generic_suspend), 928 DEVMETHOD(device_resume, bus_generic_resume), 929 930 { 0, 0 } 931}; 932 933static driver_t npx_driver = { 934 "npx", 935 npx_methods, 936 1, /* no softc */ 937}; 938 939static devclass_t npx_devclass; 940 941/* 942 * We prefer to attach to the root nexus so that the usual case (exception 16) 943 * doesn't describe the processor as being `on isa'. 944 */ 945DRIVER_MODULE(npx, nexus, npx_driver, npx_devclass, 0, 0); 946 947/* 948 * This sucks up the legacy ISA support assignments from PNPBIOS. 949 */ 950static struct isa_pnp_id npxisa_ids[] = { 951 { 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */ 952 { 0 } 953}; 954 955static int 956npxisa_probe(device_t dev) 957{ 958 int result; 959 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) { 960 device_quiet(dev); 961 } 962 return(result); 963} 964 965static int 966npxisa_attach(device_t dev) 967{ 968 return (0); 969} 970 971static device_method_t npxisa_methods[] = { 972 /* Device interface */ 973 DEVMETHOD(device_probe, npxisa_probe), 974 DEVMETHOD(device_attach, npxisa_attach), 975 DEVMETHOD(device_detach, bus_generic_detach), 976 DEVMETHOD(device_shutdown, bus_generic_shutdown), 977 DEVMETHOD(device_suspend, bus_generic_suspend), 978 DEVMETHOD(device_resume, bus_generic_resume), 979 980 { 0, 0 } 981}; 982 983static driver_t npxisa_driver = { 984 "npxisa", 985 npxisa_methods, 986 1, /* no softc */ 987}; 988 989static devclass_t npxisa_devclass; 990 991DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0); 992
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