1/*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 *
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26 * $FreeBSD: head/sys/i386/include/intr_machdep.h 153146 2005-12-05 22:39:09Z jhb $
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26 * $FreeBSD: head/sys/i386/include/intr_machdep.h 156124 2006-02-28 22:24:55Z jhb $ |
27 */ 28 29#ifndef __MACHINE_INTR_MACHDEP_H__ 30#define __MACHINE_INTR_MACHDEP_H__ 31 32#ifdef _KERNEL 33 34/* 35 * The maximum number of I/O interrupts we allow. This number is rather 36 * arbitrary as it is just the maximum IRQ resource value. The interrupt 37 * source for a given IRQ maps that I/O interrupt to device interrupt 38 * source whether it be a pin on an interrupt controller or an MSI interrupt. 39 * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device 40 * interrupts allocate IDT vectors on demand. Currently we have 191 IDT 41 * vectors available for device interrupts. On many systems with I/O APICs, 42 * a lot of the IRQs are not used, so this number can be much larger than 43 * 191 and still be safe since only interrupt sources in actual use will 44 * allocate IDT vectors. 45 * 46 * For now we stick with 255 as ISA IRQs and PCI intline IRQs only allow 47 * for IRQs in the range 0 - 254. When MSI support is added this number 48 * will likely increase. 49 */ 50#define NUM_IO_INTS 255 51 52/* 53 * - 1 ??? dummy counter. 54 * - 2 counters for each I/O interrupt. 55 * - 1 counter for each CPU for lapic timer. 56 * - 7 counters for each CPU for IPI counters for SMP. 57 */ 58#ifdef SMP 59#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1) 60#else 61#define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 7) * MAXCPU) 62#endif 63 64#ifndef LOCORE 65 66typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss); 67 68#define IDTVEC(name) __CONCAT(X,name) 69 70struct intsrc; 71 72/* 73 * Methods that a PIC provides to mask/unmask a given interrupt source, 74 * "turn on" the interrupt on the CPU side by setting up an IDT entry, and 75 * return the vector associated with this source. 76 */ 77struct pic { 78 void (*pic_enable_source)(struct intsrc *); 79 void (*pic_disable_source)(struct intsrc *, int); 80 void (*pic_eoi_source)(struct intsrc *); 81 void (*pic_enable_intr)(struct intsrc *); 82 int (*pic_vector)(struct intsrc *); 83 int (*pic_source_pending)(struct intsrc *); 84 void (*pic_suspend)(struct intsrc *); 85 void (*pic_resume)(struct intsrc *); 86 int (*pic_config_intr)(struct intsrc *, enum intr_trigger, 87 enum intr_polarity);
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88 void (*pic_assign_cpu)(struct intsrc *, u_int apic_id); |
89}; 90 91/* Flags for pic_disable_source() */ 92enum { 93 PIC_EOI, 94 PIC_NO_EOI, 95}; 96 97/* 98 * An interrupt source. The upper-layer code uses the PIC methods to 99 * control a given source. The lower-layer PIC drivers can store additional 100 * private data in a given interrupt source such as an interrupt pin number 101 * or an I/O APIC pointer. 102 */ 103struct intsrc { 104 struct pic *is_pic; 105 struct intr_event *is_event; 106 u_long *is_count; 107 u_long *is_straycount; 108 u_int is_index;
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109 u_int is_enabled:1; |
110}; 111 112struct trapframe; 113 114extern struct mtx icu_lock; 115extern int elcr_found; 116 117/* XXX: The elcr_* prototypes probably belong somewhere else. */ 118int elcr_probe(void); 119enum intr_trigger elcr_read_trigger(u_int irq); 120void elcr_resume(void); 121void elcr_write_trigger(u_int irq, enum intr_trigger trigger);
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122#ifdef SMP 123void intr_add_cpu(u_int apic_id); 124#else 125#define intr_add_cpu(apic_id) 126#endif |
127int intr_add_handler(const char *name, int vector, driver_intr_t handler, 128 void *arg, enum intr_type flags, void **cookiep); 129int intr_config_intr(int vector, enum intr_trigger trig, 130 enum intr_polarity pol); 131void intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame); 132struct intsrc *intr_lookup_source(int vector); 133int intr_register_source(struct intsrc *isrc); 134int intr_remove_handler(void *cookie); 135void intr_resume(void); 136void intr_suspend(void); 137void intrcnt_add(const char *name, u_long **countp); 138 139#endif /* !LOCORE */ 140#endif /* _KERNEL */ 141#endif /* !__MACHINE_INTR_MACHDEP_H__ */
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