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mt8127.dtsi (279385) mt8127.dtsi (295436)
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Joe.C <yingjoe.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *

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18
19/ {
20 compatible = "mediatek,mt8127";
21 interrupt-parent = <&sysirq>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Joe.C <yingjoe.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *

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18
19/ {
20 compatible = "mediatek,mt8127";
21 interrupt-parent = <&sysirq>;
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "mediatek,mt81xx-tz-smp";
26
27 cpu@0 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a7";
30 reg = <0x0>;
31 };
32 cpu@1 {
33 device_type = "cpu";

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42 cpu@3 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a7";
45 reg = <0x3>;
46 };
47
48 };
49
27
28 cpu@0 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a7";
31 reg = <0x0>;
32 };
33 cpu@1 {
34 device_type = "cpu";

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43 cpu@3 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a7";
46 reg = <0x3>;
47 };
48
49 };
50
51 reserved-memory {
52 #address-cells = <2>;
53 #size-cells = <2>;
54 ranges;
55
56 trustzone-bootinfo@80002000 {
57 compatible = "mediatek,trustzone-bootinfo";
58 reg = <0 0x80002000 0 0x1000>;
59 };
60 };
61
50 clocks {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 compatible = "simple-bus";
54 ranges;
55
56 system_clk: dummy13m {
57 compatible = "fixed-clock";

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67
68 uart_clk: dummy26m {
69 compatible = "fixed-clock";
70 clock-frequency = <26000000>;
71 #clock-cells = <0>;
72 };
73 };
74
62 clocks {
63 #address-cells = <2>;
64 #size-cells = <2>;
65 compatible = "simple-bus";
66 ranges;
67
68 system_clk: dummy13m {
69 compatible = "fixed-clock";

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79
80 uart_clk: dummy26m {
81 compatible = "fixed-clock";
82 clock-frequency = <26000000>;
83 #clock-cells = <0>;
84 };
85 };
86
87 timer {
88 compatible = "arm,armv7-timer";
89 interrupt-parent = <&gic>;
90 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
91 IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
93 IRQ_TYPE_LEVEL_LOW)>,
94 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
95 IRQ_TYPE_LEVEL_LOW)>,
96 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
97 IRQ_TYPE_LEVEL_LOW)>;
98 clock-frequency = <13000000>;
99 arm,cpu-registers-not-fw-configured;
100 };
101
75 soc {
76 #address-cells = <2>;
77 #size-cells = <2>;
78 compatible = "simple-bus";
79 ranges;
80
81 timer: timer@10008000 {
82 compatible = "mediatek,mt8127-timer",

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102 #interrupt-cells = <3>;
103 interrupt-parent = <&gic>;
104 reg = <0 0x10211000 0 0x1000>,
105 <0 0x10212000 0 0x1000>,
106 <0 0x10214000 0 0x2000>,
107 <0 0x10216000 0 0x2000>;
108 };
109
102 soc {
103 #address-cells = <2>;
104 #size-cells = <2>;
105 compatible = "simple-bus";
106 ranges;
107
108 timer: timer@10008000 {
109 compatible = "mediatek,mt8127-timer",

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129 #interrupt-cells = <3>;
130 interrupt-parent = <&gic>;
131 reg = <0 0x10211000 0 0x1000>,
132 <0 0x10212000 0 0x1000>,
133 <0 0x10214000 0 0x2000>,
134 <0 0x10216000 0 0x2000>;
135 };
136
110 uart0: serial@11006000 {
137 uart0: serial@11002000 {
111 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
112 reg = <0 0x11002000 0 0x400>;
113 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
114 clocks = <&uart_clk>;
115 status = "disabled";
116 };
117
138 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
139 reg = <0 0x11002000 0 0x400>;
140 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
141 clocks = <&uart_clk>;
142 status = "disabled";
143 };
144
118 uart1: serial@11007000 {
145 uart1: serial@11003000 {
119 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
120 reg = <0 0x11003000 0 0x400>;
121 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
122 clocks = <&uart_clk>;
123 status = "disabled";
124 };
125
146 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
147 reg = <0 0x11003000 0 0x400>;
148 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
149 clocks = <&uart_clk>;
150 status = "disabled";
151 };
152
126 uart2: serial@11008000 {
153 uart2: serial@11004000 {
127 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
128 reg = <0 0x11004000 0 0x400>;
129 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
130 clocks = <&uart_clk>;
131 status = "disabled";
132 };
133
154 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
155 reg = <0 0x11004000 0 0x400>;
156 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
157 clocks = <&uart_clk>;
158 status = "disabled";
159 };
160
134 uart3: serial@11009000 {
161 uart3: serial@11005000 {
135 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
136 reg = <0 0x11005000 0 0x400>;
137 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
138 clocks = <&uart_clk>;
139 status = "disabled";
140 };
141 };
142};
162 compatible = "mediatek,mt8127-uart","mediatek,mt6577-uart";
163 reg = <0 0x11005000 0 0x400>;
164 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
165 clocks = <&uart_clk>;
166 status = "disabled";
167 };
168 };
169};