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imx25-pdk.dts (279385) imx25-pdk.dts (295436)
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
14#include "imx25.dtsi"
15
16/ {
17 model = "Freescale i.MX25 Product Development Kit";
18 compatible = "fsl,imx25-pdk", "fsl,imx25";
19
20 memory {

--- 49 unchanged lines hidden (view full) ---

70 audio-codec = <&codec>;
71 audio-routing =
72 "MIC_IN", "Mic Jack",
73 "Mic Jack", "Mic Bias",
74 "Headphone Jack", "HP_OUT";
75 mux-int-port = <1>;
76 mux-ext-port = <4>;
77 };
14#include <dt-bindings/input/input.h>
15#include "imx25.dtsi"
16
17/ {
18 model = "Freescale i.MX25 Product Development Kit";
19 compatible = "fsl,imx25-pdk", "fsl,imx25";
20
21 memory {

--- 49 unchanged lines hidden (view full) ---

71 audio-codec = <&codec>;
72 audio-routing =
73 "MIC_IN", "Mic Jack",
74 "Mic Jack", "Mic Bias",
75 "Headphone Jack", "HP_OUT";
76 mux-int-port = <1>;
77 mux-ext-port = <4>;
78 };
79
80 wvga: display {
81 model = "CLAA057VC01CW";
82 bits-per-pixel = <16>;
83 fsl,pcr = <0xfa208b80>;
84 bus-width = <18>;
85 native-mode = <&wvga_timings>;
86 display-timings {
87 wvga_timings: 640x480 {
88 hactive = <640>;
89 vactive = <480>;
90 hback-porch = <45>;
91 hfront-porch = <114>;
92 hsync-len = <1>;
93 vback-porch = <33>;
94 vfront-porch = <11>;
95 vsync-len = <1>;
96 clock-frequency = <25200000>;
97 };
98 };
99 };
78};
79
80&audmux {
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_audmux>;
83 status = "okay";
84};
85
86&can1 {
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_can1>;
89 xceiver-supply = <&reg_can_3v3>;
90 status = "okay";
91};
92
93&esdhc1 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_esdhc1>;
100};
101
102&audmux {
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_audmux>;
105 status = "okay";
106};
107
108&can1 {
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_can1>;
111 xceiver-supply = <&reg_can_3v3>;
112 status = "okay";
113};
114
115&esdhc1 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_esdhc1>;
96 cd-gpios = <&gpio2 1 0>;
97 wp-gpios = <&gpio2 0 0>;
118 cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
119 wp-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
98 status = "okay";
99};
100
101&fec {
102 phy-mode = "rmii";
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_fec>;
105 phy-supply = <&reg_fec_3v3>;

--- 79 unchanged lines hidden (view full) ---

185 MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000
186 MX25_PAD_KPP_COL0__KPP_COL0 0x80000000
187 MX25_PAD_KPP_COL1__KPP_COL1 0x80000000
188 MX25_PAD_KPP_COL2__KPP_COL2 0x80000000
189 MX25_PAD_KPP_COL3__KPP_COL3 0x80000000
190 >;
191 };
192
120 status = "okay";
121};
122
123&fec {
124 phy-mode = "rmii";
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_fec>;
127 phy-supply = <&reg_fec_3v3>;

--- 79 unchanged lines hidden (view full) ---

207 MX25_PAD_KPP_ROW3__KPP_ROW3 0x80000000
208 MX25_PAD_KPP_COL0__KPP_COL0 0x80000000
209 MX25_PAD_KPP_COL1__KPP_COL1 0x80000000
210 MX25_PAD_KPP_COL2__KPP_COL2 0x80000000
211 MX25_PAD_KPP_COL3__KPP_COL3 0x80000000
212 >;
213 };
214
215 pinctrl_lcd: lcdgrp {
216 fsl,pins = <
217 MX25_PAD_LD0__LD0 0xe0
218 MX25_PAD_LD1__LD1 0xe0
219 MX25_PAD_LD2__LD2 0xe0
220 MX25_PAD_LD3__LD3 0xe0
221 MX25_PAD_LD4__LD4 0xe0
222 MX25_PAD_LD5__LD5 0xe0
223 MX25_PAD_LD6__LD6 0xe0
224 MX25_PAD_LD7__LD7 0xe0
225 MX25_PAD_LD8__LD8 0xe0
226 MX25_PAD_LD9__LD9 0xe0
227 MX25_PAD_LD10__LD10 0xe0
228 MX25_PAD_LD11__LD11 0xe0
229 MX25_PAD_LD12__LD12 0xe0
230 MX25_PAD_LD13__LD13 0xe0
231 MX25_PAD_LD14__LD14 0xe0
232 MX25_PAD_LD15__LD15 0xe0
233 MX25_PAD_GPIO_E__LD16 0xe0
234 MX25_PAD_GPIO_F__LD17 0xe0
235 MX25_PAD_HSYNC__HSYNC 0xe0
236 MX25_PAD_VSYNC__VSYNC 0xe0
237 MX25_PAD_LSCLK__LSCLK 0xe0
238 MX25_PAD_OE_ACD__OE_ACD 0xe0
239 MX25_PAD_CONTRAST__CONTRAST 0xe0
240 >;
241 };
193
194 pinctrl_uart1: uart1grp {
195 fsl,pins = <
196 MX25_PAD_UART1_RTS__UART1_RTS 0xe0
197 MX25_PAD_UART1_CTS__UART1_CTS 0xe0
198 MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
199 MX25_PAD_UART1_RXD__UART1_RXD 0xc0
200 >;
201 };
202 };
203};
204
242
243 pinctrl_uart1: uart1grp {
244 fsl,pins = <
245 MX25_PAD_UART1_RTS__UART1_RTS 0xe0
246 MX25_PAD_UART1_CTS__UART1_CTS 0xe0
247 MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
248 MX25_PAD_UART1_RXD__UART1_RXD 0xc0
249 >;
250 };
251 };
252};
253
254&lcdc {
255 display = <&wvga>;
256 fsl,lpccr = <0x00a903ff>;
257 fsl,lscr1 = <0x00120300>;
258 fsl,dmacr = <0x00020010>;
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_lcd>;
261 status = "okay";
262};
263
205&nfc {
206 nand-on-flash-bbt;
207 status = "okay";
208};
209
210&kpp {
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_kpp>;

--- 45 unchanged lines hidden --- 		264&nfc {
265 nand-on-flash-bbt;
266 status = "okay";
267};
268
269&kpp {
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_kpp>;

--- 45 unchanged lines hidden ---