1/*
2 * Hisilicon Ltd. HiP04 SoC
3 *
4 * Copyright (C) 2013-2014 Hisilicon Ltd.
5 * Copyright (C) 2013-2014 Linaro Ltd.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 *

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270 };
271
272 };
273
274 etb@0,e3c42000 {
275 compatible = "arm,coresight-etb10", "arm,primecell";
276 reg = <0 0xe3c42000 0 0x1000>;
277
278 coresight-default-sink;
279 clocks = <&clk_375m>;
280 clock-names = "apb_pclk";
281 port {
282 etb0_in_port: endpoint@0 {
283 slave-mode;
284 remote-endpoint = <&replicator0_out_port0>;
285 };
286 };

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