1/*
2 * SAMSUNG EXYNOS5440 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as

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214 };
215
216 tmuctrl_0: tmuctrl@160118 {
217 compatible = "samsung,exynos5440-tmu";
218 reg = <0x160118 0x230>, <0x160368 0x10>;
219 interrupts = <0 58 0>;
220 clocks = <&clock CLK_B_125>;
221 clock-names = "tmu_apbif";
222 };
223
224 tmuctrl_1: tmuctrl@16011C {
225 compatible = "samsung,exynos5440-tmu";
226 reg = <0x16011C 0x230>, <0x160368 0x10>;
227 interrupts = <0 58 0>;
228 clocks = <&clock CLK_B_125>;
229 clock-names = "tmu_apbif";
230 };
231
232 tmuctrl_2: tmuctrl@160120 {
233 compatible = "samsung,exynos5440-tmu";
234 reg = <0x160120 0x230>, <0x160368 0x10>;
235 interrupts = <0 58 0>;
236 clocks = <&clock CLK_B_125>;
237 clock-names = "tmu_apbif";
238 };
239
240 sata@210000 {
241 compatible = "snps,exynos5440-ahci";
242 reg = <0x210000 0x10000>;
243 interrupts = <0 30 0>;
244 clocks = <&clock CLK_SATA>;
245 clock-names = "sata";
246 };
247

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256 ehci@221000 {
257 compatible = "samsung,exynos5440-ehci";
258 reg = <0x221000 0x1000>;
259 interrupts = <0 29 0>;
260 clocks = <&clock CLK_USB>;
261 clock-names = "usbhost";
262 };
263
264 pcie@290000 {
265 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
266 reg = <0x290000 0x1000
267 0x270000 0x1000
268 0x271000 0x40>;
269 interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
270 clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
271 clock-names = "pcie", "pcie_bus";
272 #address-cells = <3>;

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277 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
278 #interrupt-cells = <1>;
279 interrupt-map-mask = <0 0 0 0>;
280 interrupt-map = <0x0 0 &gic 53>;
281 num-lanes = <4>;
282 status = "disabled";
283 };
284
285 pcie@2a0000 {
286 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
287 reg = <0x2a0000 0x1000
288 0x272000 0x1000
289 0x271040 0x40>;
290 interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
291 clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
292 clock-names = "pcie", "pcie_bus";
293 #address-cells = <3>;

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