exynos4415.dtsi (279385) | exynos4415.dtsi (295436) |
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1/* 2 * Samsung's Exynos4415 SoC device tree source 3 * 4 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 5 * 6 * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415 7 * based board files can include this file and provide values for board 8 * specific bindings. --- 110 unchanged lines hidden (view full) --- 119 120 pmu_system_controller: system-controller@10020000 { 121 compatible = "samsung,exynos4415-pmu", "syscon"; 122 reg = <0x10020000 0x4000>; 123 }; 124 125 mipi_phy: video-phy@10020710 { 126 compatible = "samsung,s5pv210-mipi-video-phy"; | 1/* 2 * Samsung's Exynos4415 SoC device tree source 3 * 4 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 5 * 6 * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415 7 * based board files can include this file and provide values for board 8 * specific bindings. --- 110 unchanged lines hidden (view full) --- 119 120 pmu_system_controller: system-controller@10020000 { 121 compatible = "samsung,exynos4415-pmu", "syscon"; 122 reg = <0x10020000 0x4000>; 123 }; 124 125 mipi_phy: video-phy@10020710 { 126 compatible = "samsung,s5pv210-mipi-video-phy"; |
127 reg = <0x10020710 8>; | |
128 #phy-cells = <1>; | 127 #phy-cells = <1>; |
128 syscon = <&pmu_system_controller>; |
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129 }; 130 131 pd_cam: cam-power-domain@10024000 { 132 compatible = "samsung,exynos4210-pd"; 133 reg = <0x10024000 0x20>; 134 #power-domain-cells = <0>; 135 }; 136 --- 35 unchanged lines hidden (view full) --- 172 173 cmu: clock-controller@10030000 { 174 compatible = "samsung,exynos4415-cmu"; 175 reg = <0x10030000 0x18000>; 176 #clock-cells = <1>; 177 }; 178 179 rtc: rtc@10070000 { | 129 }; 130 131 pd_cam: cam-power-domain@10024000 { 132 compatible = "samsung,exynos4210-pd"; 133 reg = <0x10024000 0x20>; 134 #power-domain-cells = <0>; 135 }; 136 --- 35 unchanged lines hidden (view full) --- 172 173 cmu: clock-controller@10030000 { 174 compatible = "samsung,exynos4415-cmu"; 175 reg = <0x10030000 0x18000>; 176 #clock-cells = <1>; 177 }; 178 179 rtc: rtc@10070000 { |
180 compatible = "samsung,exynos3250-rtc"; | 180 compatible = "samsung,s3c6410-rtc"; |
181 reg = <0x10070000 0x100>; 182 interrupts = <0 73 0>, <0 74 0>; 183 status = "disabled"; 184 }; 185 186 mct@10050000 { 187 compatible = "samsung,exynos4210-mct"; 188 reg = <0x10050000 0x800>; --- 55 unchanged lines hidden (view full) --- 244 fimd: fimd@11C00000 { 245 compatible = "samsung,exynos4415-fimd"; 246 reg = <0x11C00000 0x30000>; 247 interrupt-names = "fifo", "vsync", "lcd_sys"; 248 interrupts = <0 84 0>, <0 85 0>, <0 86 0>; 249 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; 250 clock-names = "sclk_fimd", "fimd"; 251 samsung,power-domain = <&pd_lcd0>; | 181 reg = <0x10070000 0x100>; 182 interrupts = <0 73 0>, <0 74 0>; 183 status = "disabled"; 184 }; 185 186 mct@10050000 { 187 compatible = "samsung,exynos4210-mct"; 188 reg = <0x10050000 0x800>; --- 55 unchanged lines hidden (view full) --- 244 fimd: fimd@11C00000 { 245 compatible = "samsung,exynos4415-fimd"; 246 reg = <0x11C00000 0x30000>; 247 interrupt-names = "fifo", "vsync", "lcd_sys"; 248 interrupts = <0 84 0>, <0 85 0>, <0 86 0>; 249 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; 250 clock-names = "sclk_fimd", "fimd"; 251 samsung,power-domain = <&pd_lcd0>; |
252 iommus = <&sysmmu_fimd0>; |
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252 samsung,sysreg = <&sysreg_system_controller>; 253 status = "disabled"; 254 }; 255 256 dsi_0: dsi@11C80000 { 257 compatible = "samsung,exynos4415-mipi-dsi"; 258 reg = <0x11C80000 0x10000>; 259 interrupts = <0 83 0>; 260 samsung,phy-type = <0>; 261 samsung,power-domain = <&pd_lcd0>; 262 phys = <&mipi_phy 1>; 263 phy-names = "dsim"; 264 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; 265 clock-names = "bus_clk", "pll_clk"; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 status = "disabled"; 269 }; 270 | 253 samsung,sysreg = <&sysreg_system_controller>; 254 status = "disabled"; 255 }; 256 257 dsi_0: dsi@11C80000 { 258 compatible = "samsung,exynos4415-mipi-dsi"; 259 reg = <0x11C80000 0x10000>; 260 interrupts = <0 83 0>; 261 samsung,phy-type = <0>; 262 samsung,power-domain = <&pd_lcd0>; 263 phys = <&mipi_phy 1>; 264 phy-names = "dsim"; 265 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; 266 clock-names = "bus_clk", "pll_clk"; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 status = "disabled"; 270 }; 271 |
272 sysmmu_fimd0: sysmmu@11E20000 { 273 compatible = "samsung,exynos-sysmmu"; 274 reg = <0x11e20000 0x1000>; 275 interrupts = <0 80 0>, <0 81 0>; 276 clock-names = "sysmmu", "master"; 277 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>; 278 power-domains = <&pd_lcd0>; 279 #iommu-cells = <0>; 280 }; 281 |
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271 hsotg: hsotg@12480000 { 272 compatible = "samsung,s3c6400-hsotg"; 273 reg = <0x12480000 0x20000>; 274 interrupts = <0 141 0>; 275 clocks = <&cmu CLK_USBDEVICE>; 276 clock-names = "otg"; 277 phys = <&exynos_usbphy 0>; 278 phy-names = "usb2-phy"; --- 360 unchanged lines hidden --- | 282 hsotg: hsotg@12480000 { 283 compatible = "samsung,s3c6400-hsotg"; 284 reg = <0x12480000 0x20000>; 285 interrupts = <0 141 0>; 286 clocks = <&cmu CLK_USBDEVICE>; 287 clock-names = "otg"; 288 phys = <&exynos_usbphy 0>; 289 phy-names = "usb2-phy"; --- 360 unchanged lines hidden --- |