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exynos4.dtsi (279385) exynos4.dtsi (295436)
1/*
2 * Samsung's Exynos4 SoC series common device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *

--- 24 unchanged lines hidden (view full) ---

33 i2c0 = &i2c_0;
34 i2c1 = &i2c_1;
35 i2c2 = &i2c_2;
36 i2c3 = &i2c_3;
37 i2c4 = &i2c_4;
38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7;
1/*
2 * Samsung's Exynos4 SoC series common device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *

--- 24 unchanged lines hidden (view full) ---

33 i2c0 = &i2c_0;
34 i2c1 = &i2c_1;
35 i2c2 = &i2c_2;
36 i2c3 = &i2c_3;
37 i2c4 = &i2c_4;
38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7;
41 i2c8 = &i2c_8;
41 csis0 = &csis_0;
42 csis1 = &csis_1;
43 fimc0 = &fimc_0;
44 fimc1 = &fimc_1;
45 fimc2 = &fimc_2;
46 fimc3 = &fimc_3;
47 serial0 = &serial_0;
48 serial1 = &serial_1;

--- 23 unchanged lines hidden (view full) ---

72
73 chipid@10000000 {
74 compatible = "samsung,exynos4210-chipid";
75 reg = <0x10000000 0x100>;
76 };
77
78 mipi_phy: video-phy@10020710 {
79 compatible = "samsung,s5pv210-mipi-video-phy";
42 csis0 = &csis_0;
43 csis1 = &csis_1;
44 fimc0 = &fimc_0;
45 fimc1 = &fimc_1;
46 fimc2 = &fimc_2;
47 fimc3 = &fimc_3;
48 serial0 = &serial_0;
49 serial1 = &serial_1;

--- 23 unchanged lines hidden (view full) ---

73
74 chipid@10000000 {
75 compatible = "samsung,exynos4210-chipid";
76 reg = <0x10000000 0x100>;
77 };
78
79 mipi_phy: video-phy@10020710 {
80 compatible = "samsung,s5pv210-mipi-video-phy";
80 reg = <0x10020710 8>;
81 #phy-cells = <1>;
82 syscon = <&pmu_system_controller>;
83 };
84
85 pd_mfc: mfc-power-domain@10023C40 {
86 compatible = "samsung,exynos4210-pd";
87 reg = <0x10023C40 0x20>;
88 #power-domain-cells = <0>;

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99 reg = <0x10023C80 0x20>;
100 #power-domain-cells = <0>;
101 };
102
103 pd_tv: tv-power-domain@10023C20 {
104 compatible = "samsung,exynos4210-pd";
105 reg = <0x10023C20 0x20>;
106 #power-domain-cells = <0>;
81 #phy-cells = <1>;
82 syscon = <&pmu_system_controller>;
83 };
84
85 pd_mfc: mfc-power-domain@10023C40 {
86 compatible = "samsung,exynos4210-pd";
87 reg = <0x10023C40 0x20>;
88 #power-domain-cells = <0>;

--- 10 unchanged lines hidden (view full) ---

99 reg = <0x10023C80 0x20>;
100 #power-domain-cells = <0>;
101 };
102
103 pd_tv: tv-power-domain@10023C20 {
104 compatible = "samsung,exynos4210-pd";
105 reg = <0x10023C20 0x20>;
106 #power-domain-cells = <0>;
107 power-domains = <&pd_lcd0>;
107 };
108
109 pd_cam: cam-power-domain@10023C00 {
110 compatible = "samsung,exynos4210-pd";
111 reg = <0x10023C00 0x20>;
112 #power-domain-cells = <0>;
113 };
114

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147 sys_reg: syscon@10010000 {
148 compatible = "samsung,exynos4-sysreg", "syscon";
149 reg = <0x10010000 0x400>;
150 };
151
152 pmu_system_controller: system-controller@10020000 {
153 compatible = "samsung,exynos4210-pmu", "syscon";
154 reg = <0x10020000 0x4000>;
108 };
109
110 pd_cam: cam-power-domain@10023C00 {
111 compatible = "samsung,exynos4210-pd";
112 reg = <0x10023C00 0x20>;
113 #power-domain-cells = <0>;
114 };
115

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148 sys_reg: syscon@10010000 {
149 compatible = "samsung,exynos4-sysreg", "syscon";
150 reg = <0x10010000 0x400>;
151 };
152
153 pmu_system_controller: system-controller@10020000 {
154 compatible = "samsung,exynos4210-pmu", "syscon";
155 reg = <0x10020000 0x4000>;
156 interrupt-controller;
157 #interrupt-cells = <3>;
158 interrupt-parent = <&gic>;
155 };
156
159 };
160
161 poweroff: syscon-poweroff {
162 compatible = "syscon-poweroff";
163 regmap = <&pmu_system_controller>;
164 offset = <0x330C>; /* PS_HOLD_CONTROL */
165 mask = <0x5200>; /* reset value */
166 };
167
168 reboot: syscon-reboot {
169 compatible = "syscon-reboot";
170 regmap = <&pmu_system_controller>;
171 offset = <0x0400>; /* SWRESET */
172 mask = <0x1>;
173 };
174
157 dsi_0: dsi@11C80000 {
158 compatible = "samsung,exynos4210-mipi-dsi";
159 reg = <0x11C80000 0x10000>;
160 interrupts = <0 79 0>;
161 power-domains = <&pd_lcd0>;
162 phys = <&mipi_phy 1>;
163 phy-names = "dsim";
164 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
175 dsi_0: dsi@11C80000 {
176 compatible = "samsung,exynos4210-mipi-dsi";
177 reg = <0x11C80000 0x10000>;
178 interrupts = <0 79 0>;
179 power-domains = <&pd_lcd0>;
180 phys = <&mipi_phy 1>;
181 phy-names = "dsim";
182 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
165 clock-names = "bus_clk", "pll_clk";
183 clock-names = "bus_clk", "sclk_mipi";
166 status = "disabled";
167 #address-cells = <1>;
168 #size-cells = <0>;
169 };
170
171 camera {
172 compatible = "samsung,fimc", "simple-bus";
173 status = "disabled";

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180 fimc_0: fimc@11800000 {
181 compatible = "samsung,exynos4210-fimc";
182 reg = <0x11800000 0x1000>;
183 interrupts = <0 84 0>;
184 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
185 clock-names = "fimc", "sclk_fimc";
186 power-domains = <&pd_cam>;
187 samsung,sysreg = <&sys_reg>;
184 status = "disabled";
185 #address-cells = <1>;
186 #size-cells = <0>;
187 };
188
189 camera {
190 compatible = "samsung,fimc", "simple-bus";
191 status = "disabled";

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198 fimc_0: fimc@11800000 {
199 compatible = "samsung,exynos4210-fimc";
200 reg = <0x11800000 0x1000>;
201 interrupts = <0 84 0>;
202 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
203 clock-names = "fimc", "sclk_fimc";
204 power-domains = <&pd_cam>;
205 samsung,sysreg = <&sys_reg>;
206 iommus = <&sysmmu_fimc0>;
188 status = "disabled";
189 };
190
191 fimc_1: fimc@11810000 {
192 compatible = "samsung,exynos4210-fimc";
193 reg = <0x11810000 0x1000>;
194 interrupts = <0 85 0>;
195 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
196 clock-names = "fimc", "sclk_fimc";
197 power-domains = <&pd_cam>;
198 samsung,sysreg = <&sys_reg>;
207 status = "disabled";
208 };
209
210 fimc_1: fimc@11810000 {
211 compatible = "samsung,exynos4210-fimc";
212 reg = <0x11810000 0x1000>;
213 interrupts = <0 85 0>;
214 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
215 clock-names = "fimc", "sclk_fimc";
216 power-domains = <&pd_cam>;
217 samsung,sysreg = <&sys_reg>;
218 iommus = <&sysmmu_fimc1>;
199 status = "disabled";
200 };
201
202 fimc_2: fimc@11820000 {
203 compatible = "samsung,exynos4210-fimc";
204 reg = <0x11820000 0x1000>;
205 interrupts = <0 86 0>;
206 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
207 clock-names = "fimc", "sclk_fimc";
208 power-domains = <&pd_cam>;
209 samsung,sysreg = <&sys_reg>;
219 status = "disabled";
220 };
221
222 fimc_2: fimc@11820000 {
223 compatible = "samsung,exynos4210-fimc";
224 reg = <0x11820000 0x1000>;
225 interrupts = <0 86 0>;
226 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
227 clock-names = "fimc", "sclk_fimc";
228 power-domains = <&pd_cam>;
229 samsung,sysreg = <&sys_reg>;
230 iommus = <&sysmmu_fimc2>;
210 status = "disabled";
211 };
212
213 fimc_3: fimc@11830000 {
214 compatible = "samsung,exynos4210-fimc";
215 reg = <0x11830000 0x1000>;
216 interrupts = <0 87 0>;
217 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
218 clock-names = "fimc", "sclk_fimc";
219 power-domains = <&pd_cam>;
220 samsung,sysreg = <&sys_reg>;
231 status = "disabled";
232 };
233
234 fimc_3: fimc@11830000 {
235 compatible = "samsung,exynos4210-fimc";
236 reg = <0x11830000 0x1000>;
237 interrupts = <0 87 0>;
238 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
239 clock-names = "fimc", "sclk_fimc";
240 power-domains = <&pd_cam>;
241 samsung,sysreg = <&sys_reg>;
242 iommus = <&sysmmu_fimc3>;
221 status = "disabled";
222 };
223
224 csis_0: csis@11880000 {
225 compatible = "samsung,exynos4210-csis";
226 reg = <0x11880000 0x4000>;
227 interrupts = <0 78 0>;
228 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;

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247 phys = <&mipi_phy 2>;
248 phy-names = "csis";
249 status = "disabled";
250 #address-cells = <1>;
251 #size-cells = <0>;
252 };
253 };
254
243 status = "disabled";
244 };
245
246 csis_0: csis@11880000 {
247 compatible = "samsung,exynos4210-csis";
248 reg = <0x11880000 0x4000>;
249 interrupts = <0 78 0>;
250 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;

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269 phys = <&mipi_phy 2>;
270 phy-names = "csis";
271 status = "disabled";
272 #address-cells = <1>;
273 #size-cells = <0>;
274 };
275 };
276
255 watchdog@10060000 {
277 watchdog: watchdog@10060000 {
256 compatible = "samsung,s3c2410-wdt";
257 reg = <0x10060000 0x100>;
258 interrupts = <0 43 0>;
259 clocks = <&clock CLK_WDT>;
260 clock-names = "watchdog";
261 status = "disabled";
262 };
263
278 compatible = "samsung,s3c2410-wdt";
279 reg = <0x10060000 0x100>;
280 interrupts = <0 43 0>;
281 clocks = <&clock CLK_WDT>;
282 clock-names = "watchdog";
283 status = "disabled";
284 };
285
264 rtc@10070000 {
286 rtc: rtc@10070000 {
265 compatible = "samsung,s3c6410-rtc";
266 reg = <0x10070000 0x100>;
287 compatible = "samsung,s3c6410-rtc";
288 reg = <0x10070000 0x100>;
289 interrupt-parent = <&pmu_system_controller>;
267 interrupts = <0 44 0>, <0 45 0>;
268 clocks = <&clock CLK_RTC>;
269 clock-names = "rtc";
270 status = "disabled";
271 };
272
290 interrupts = <0 44 0>, <0 45 0>;
291 clocks = <&clock CLK_RTC>;
292 clock-names = "rtc";
293 status = "disabled";
294 };
295
273 keypad@100A0000 {
296 keypad: keypad@100A0000 {
274 compatible = "samsung,s5pv210-keypad";
275 reg = <0x100A0000 0x100>;
276 interrupts = <0 109 0>;
277 clocks = <&clock CLK_KEYIF>;
278 clock-names = "keypad";
279 status = "disabled";
280 };
281
297 compatible = "samsung,s5pv210-keypad";
298 reg = <0x100A0000 0x100>;
299 interrupts = <0 109 0>;
300 clocks = <&clock CLK_KEYIF>;
301 clock-names = "keypad";
302 status = "disabled";
303 };
304
282 sdhci@12510000 {
305 sdhci_0: sdhci@12510000 {
283 compatible = "samsung,exynos4210-sdhci";
284 reg = <0x12510000 0x100>;
285 interrupts = <0 73 0>;
286 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
287 clock-names = "hsmmc", "mmc_busclk.2";
288 status = "disabled";
289 };
290
306 compatible = "samsung,exynos4210-sdhci";
307 reg = <0x12510000 0x100>;
308 interrupts = <0 73 0>;
309 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
310 clock-names = "hsmmc", "mmc_busclk.2";
311 status = "disabled";
312 };
313
291 sdhci@12520000 {
314 sdhci_1: sdhci@12520000 {
292 compatible = "samsung,exynos4210-sdhci";
293 reg = <0x12520000 0x100>;
294 interrupts = <0 74 0>;
295 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
296 clock-names = "hsmmc", "mmc_busclk.2";
297 status = "disabled";
298 };
299
315 compatible = "samsung,exynos4210-sdhci";
316 reg = <0x12520000 0x100>;
317 interrupts = <0 74 0>;
318 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
319 clock-names = "hsmmc", "mmc_busclk.2";
320 status = "disabled";
321 };
322
300 sdhci@12530000 {
323 sdhci_2: sdhci@12530000 {
301 compatible = "samsung,exynos4210-sdhci";
302 reg = <0x12530000 0x100>;
303 interrupts = <0 75 0>;
304 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
305 clock-names = "hsmmc", "mmc_busclk.2";
306 status = "disabled";
307 };
308
324 compatible = "samsung,exynos4210-sdhci";
325 reg = <0x12530000 0x100>;
326 interrupts = <0 75 0>;
327 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
328 clock-names = "hsmmc", "mmc_busclk.2";
329 status = "disabled";
330 };
331
309 sdhci@12540000 {
332 sdhci_3: sdhci@12540000 {
310 compatible = "samsung,exynos4210-sdhci";
311 reg = <0x12540000 0x100>;
312 interrupts = <0 76 0>;
313 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
314 clock-names = "hsmmc", "mmc_busclk.2";
315 status = "disabled";
316 };
317
318 exynos_usbphy: exynos-usbphy@125B0000 {
319 compatible = "samsung,exynos4210-usb2-phy";
320 reg = <0x125B0000 0x100>;
321 samsung,pmureg-phandle = <&pmu_system_controller>;
322 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
323 clock-names = "phy", "ref";
324 #phy-cells = <1>;
325 status = "disabled";
326 };
327
333 compatible = "samsung,exynos4210-sdhci";
334 reg = <0x12540000 0x100>;
335 interrupts = <0 76 0>;
336 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
337 clock-names = "hsmmc", "mmc_busclk.2";
338 status = "disabled";
339 };
340
341 exynos_usbphy: exynos-usbphy@125B0000 {
342 compatible = "samsung,exynos4210-usb2-phy";
343 reg = <0x125B0000 0x100>;
344 samsung,pmureg-phandle = <&pmu_system_controller>;
345 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
346 clock-names = "phy", "ref";
347 #phy-cells = <1>;
348 status = "disabled";
349 };
350
328 hsotg@12480000 {
351 hsotg: hsotg@12480000 {
329 compatible = "samsung,s3c6400-hsotg";
330 reg = <0x12480000 0x20000>;
331 interrupts = <0 71 0>;
332 clocks = <&clock CLK_USB_DEVICE>;
333 clock-names = "otg";
334 phys = <&exynos_usbphy 0>;
335 phy-names = "usb2-phy";
336 status = "disabled";
337 };
338
352 compatible = "samsung,s3c6400-hsotg";
353 reg = <0x12480000 0x20000>;
354 interrupts = <0 71 0>;
355 clocks = <&clock CLK_USB_DEVICE>;
356 clock-names = "otg";
357 phys = <&exynos_usbphy 0>;
358 phy-names = "usb2-phy";
359 status = "disabled";
360 };
361
339 ehci@12580000 {
362 ehci: ehci@12580000 {
340 compatible = "samsung,exynos4210-ehci";
341 reg = <0x12580000 0x100>;
342 interrupts = <0 70 0>;
343 clocks = <&clock CLK_USB_HOST>;
344 clock-names = "usbhost";
345 status = "disabled";
346 #address-cells = <1>;
347 #size-cells = <0>;

--- 9 unchanged lines hidden (view full) ---

357 };
358 port@2 {
359 reg = <2>;
360 phys = <&exynos_usbphy 3>;
361 status = "disabled";
362 };
363 };
364
363 compatible = "samsung,exynos4210-ehci";
364 reg = <0x12580000 0x100>;
365 interrupts = <0 70 0>;
366 clocks = <&clock CLK_USB_HOST>;
367 clock-names = "usbhost";
368 status = "disabled";
369 #address-cells = <1>;
370 #size-cells = <0>;

--- 9 unchanged lines hidden (view full) ---

380 };
381 port@2 {
382 reg = <2>;
383 phys = <&exynos_usbphy 3>;
384 status = "disabled";
385 };
386 };
387
365 ohci@12590000 {
388 ohci: ohci@12590000 {
366 compatible = "samsung,exynos4210-ohci";
367 reg = <0x12590000 0x100>;
368 interrupts = <0 70 0>;
369 clocks = <&clock CLK_USB_HOST>;
370 clock-names = "usbhost";
371 status = "disabled";
372 #address-cells = <1>;
373 #size-cells = <0>;

--- 32 unchanged lines hidden (view full) ---

406
407 mfc: codec@13400000 {
408 compatible = "samsung,mfc-v5";
409 reg = <0x13400000 0x10000>;
410 interrupts = <0 94 0>;
411 power-domains = <&pd_mfc>;
412 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
413 clock-names = "mfc", "sclk_mfc";
389 compatible = "samsung,exynos4210-ohci";
390 reg = <0x12590000 0x100>;
391 interrupts = <0 70 0>;
392 clocks = <&clock CLK_USB_HOST>;
393 clock-names = "usbhost";
394 status = "disabled";
395 #address-cells = <1>;
396 #size-cells = <0>;

--- 32 unchanged lines hidden (view full) ---

429
430 mfc: codec@13400000 {
431 compatible = "samsung,mfc-v5";
432 reg = <0x13400000 0x10000>;
433 interrupts = <0 94 0>;
434 power-domains = <&pd_mfc>;
435 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
436 clock-names = "mfc", "sclk_mfc";
437 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
438 iommu-names = "left", "right";
414 status = "disabled";
415 };
416
417 serial_0: serial@13800000 {
418 compatible = "samsung,exynos4210-uart";
419 reg = <0x13800000 0x100>;
420 interrupts = <0 52 0>;
421 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
422 clock-names = "uart", "clk_uart_baud0";
439 status = "disabled";
440 };
441
442 serial_0: serial@13800000 {
443 compatible = "samsung,exynos4210-uart";
444 reg = <0x13800000 0x100>;
445 interrupts = <0 52 0>;
446 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
447 clock-names = "uart", "clk_uart_baud0";
448 dmas = <&pdma0 15>, <&pdma0 16>;
449 dma-names = "rx", "tx";
423 status = "disabled";
424 };
425
426 serial_1: serial@13810000 {
427 compatible = "samsung,exynos4210-uart";
428 reg = <0x13810000 0x100>;
429 interrupts = <0 53 0>;
430 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
431 clock-names = "uart", "clk_uart_baud0";
450 status = "disabled";
451 };
452
453 serial_1: serial@13810000 {
454 compatible = "samsung,exynos4210-uart";
455 reg = <0x13810000 0x100>;
456 interrupts = <0 53 0>;
457 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
458 clock-names = "uart", "clk_uart_baud0";
459 dmas = <&pdma1 15>, <&pdma1 16>;
460 dma-names = "rx", "tx";
432 status = "disabled";
433 };
434
435 serial_2: serial@13820000 {
436 compatible = "samsung,exynos4210-uart";
437 reg = <0x13820000 0x100>;
438 interrupts = <0 54 0>;
439 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
440 clock-names = "uart", "clk_uart_baud0";
461 status = "disabled";
462 };
463
464 serial_2: serial@13820000 {
465 compatible = "samsung,exynos4210-uart";
466 reg = <0x13820000 0x100>;
467 interrupts = <0 54 0>;
468 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
469 clock-names = "uart", "clk_uart_baud0";
470 dmas = <&pdma0 17>, <&pdma0 18>;
471 dma-names = "rx", "tx";
441 status = "disabled";
442 };
443
444 serial_3: serial@13830000 {
445 compatible = "samsung,exynos4210-uart";
446 reg = <0x13830000 0x100>;
447 interrupts = <0 55 0>;
448 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
449 clock-names = "uart", "clk_uart_baud0";
472 status = "disabled";
473 };
474
475 serial_3: serial@13830000 {
476 compatible = "samsung,exynos4210-uart";
477 reg = <0x13830000 0x100>;
478 interrupts = <0 55 0>;
479 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
480 clock-names = "uart", "clk_uart_baud0";
481 dmas = <&pdma1 17>, <&pdma1 18>;
482 dma-names = "rx", "tx";
450 status = "disabled";
451 };
452
453 i2c_0: i2c@13860000 {
454 #address-cells = <1>;
455 #size-cells = <0>;
456 compatible = "samsung,s3c2440-i2c";
457 reg = <0x13860000 0x100>;

--- 91 unchanged lines hidden (view full) ---

549 interrupts = <0 65 0>;
550 clocks = <&clock CLK_I2C7>;
551 clock-names = "i2c";
552 pinctrl-names = "default";
553 pinctrl-0 = <&i2c7_bus>;
554 status = "disabled";
555 };
556
483 status = "disabled";
484 };
485
486 i2c_0: i2c@13860000 {
487 #address-cells = <1>;
488 #size-cells = <0>;
489 compatible = "samsung,s3c2440-i2c";
490 reg = <0x13860000 0x100>;

--- 91 unchanged lines hidden (view full) ---

582 interrupts = <0 65 0>;
583 clocks = <&clock CLK_I2C7>;
584 clock-names = "i2c";
585 pinctrl-names = "default";
586 pinctrl-0 = <&i2c7_bus>;
587 status = "disabled";
588 };
589
590 i2c_8: i2c@138E0000 {
591 #address-cells = <1>;
592 #size-cells = <0>;
593 compatible = "samsung,s3c2440-hdmiphy-i2c";
594 reg = <0x138E0000 0x100>;
595 interrupts = <0 93 0>;
596 clocks = <&clock CLK_I2C_HDMI>;
597 clock-names = "i2c";
598 status = "disabled";
599
600 hdmi_i2c_phy: hdmiphy@38 {
601 compatible = "exynos4210-hdmiphy";
602 reg = <0x38>;
603 };
604 };
605
557 spi_0: spi@13920000 {
558 compatible = "samsung,exynos4210-spi";
559 reg = <0x13920000 0x100>;
560 interrupts = <0 66 0>;
561 dmas = <&pdma0 7>, <&pdma0 6>;
562 dma-names = "tx", "rx";
563 #address-cells = <1>;
564 #size-cells = <0>;

--- 29 unchanged lines hidden (view full) ---

594 #size-cells = <0>;
595 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
596 clock-names = "spi", "spi_busclk0";
597 pinctrl-names = "default";
598 pinctrl-0 = <&spi2_bus>;
599 status = "disabled";
600 };
601
606 spi_0: spi@13920000 {
607 compatible = "samsung,exynos4210-spi";
608 reg = <0x13920000 0x100>;
609 interrupts = <0 66 0>;
610 dmas = <&pdma0 7>, <&pdma0 6>;
611 dma-names = "tx", "rx";
612 #address-cells = <1>;
613 #size-cells = <0>;

--- 29 unchanged lines hidden (view full) ---

643 #size-cells = <0>;
644 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
645 clock-names = "spi", "spi_busclk0";
646 pinctrl-names = "default";
647 pinctrl-0 = <&spi2_bus>;
648 status = "disabled";
649 };
650
602 pwm@139D0000 {
651 pwm: pwm@139D0000 {
603 compatible = "samsung,exynos4210-pwm";
604 reg = <0x139D0000 0x1000>;
605 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
606 clocks = <&clock CLK_PWM>;
607 clock-names = "timers";
608 #pwm-cells = <3>;
609 status = "disabled";
610 };

--- 43 unchanged lines hidden (view full) ---

654 compatible = "samsung,exynos4210-fimd";
655 interrupt-parent = <&combiner>;
656 reg = <0x11c00000 0x20000>;
657 interrupt-names = "fifo", "vsync", "lcd_sys";
658 interrupts = <11 0>, <11 1>, <11 2>;
659 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
660 clock-names = "sclk_fimd", "fimd";
661 power-domains = <&pd_lcd0>;
652 compatible = "samsung,exynos4210-pwm";
653 reg = <0x139D0000 0x1000>;
654 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
655 clocks = <&clock CLK_PWM>;
656 clock-names = "timers";
657 #pwm-cells = <3>;
658 status = "disabled";
659 };

--- 43 unchanged lines hidden (view full) ---

703 compatible = "samsung,exynos4210-fimd";
704 interrupt-parent = <&combiner>;
705 reg = <0x11c00000 0x20000>;
706 interrupt-names = "fifo", "vsync", "lcd_sys";
707 interrupts = <11 0>, <11 1>, <11 2>;
708 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
709 clock-names = "sclk_fimd", "fimd";
710 power-domains = <&pd_lcd0>;
711 iommus = <&sysmmu_fimd0>;
662 samsung,sysreg = <&sys_reg>;
663 status = "disabled";
664 };
665
712 samsung,sysreg = <&sys_reg>;
713 status = "disabled";
714 };
715
716 tmu: tmu@100C0000 {
717 #include "exynos4412-tmu-sensor-conf.dtsi"
718 };
719
720 jpeg_codec: jpeg-codec@11840000 {
721 compatible = "samsung,exynos4210-jpeg";
722 reg = <0x11840000 0x1000>;
723 interrupts = <0 88 0>;
724 clocks = <&clock CLK_JPEG>;
725 clock-names = "jpeg";
726 power-domains = <&pd_cam>;
727 iommus = <&sysmmu_jpeg>;
728 };
729
730 rotator: rotator@12810000 {
731 compatible = "samsung,exynos4210-rotator";
732 reg = <0x12810000 0x64>;
733 interrupts = <0 83 0>;
734 clocks = <&clock CLK_ROTATOR>;
735 clock-names = "rotator";
736 iommus = <&sysmmu_rotator>;
737 };
738
739 hdmi: hdmi@12D00000 {
740 compatible = "samsung,exynos4210-hdmi";
741 reg = <0x12D00000 0x70000>;
742 interrupts = <0 92 0>;
743 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
744 "mout_hdmi";
745 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
746 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
747 <&clock CLK_MOUT_HDMI>;
748 phy = <&hdmi_i2c_phy>;
749 power-domains = <&pd_tv>;
750 samsung,syscon-phandle = <&pmu_system_controller>;
751 status = "disabled";
752 };
753
754 mixer: mixer@12C10000 {
755 compatible = "samsung,exynos4210-mixer";
756 interrupts = <0 91 0>;
757 reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
758 power-domains = <&pd_tv>;
759 iommus = <&sysmmu_tv>;
760 status = "disabled";
761 };
762
666 ppmu_dmc0: ppmu_dmc0@106a0000 {
667 compatible = "samsung,exynos-ppmu";
668 reg = <0x106a0000 0x2000>;
669 clocks = <&clock CLK_PPMUDMC0>;
670 clock-names = "ppmu";
671 status = "disabled";
672 };
673

--- 91 unchanged lines hidden (view full) ---

765
766 ppmu_mfc_right: ppmu_mfc_right@13670000 {
767 compatible = "samsung,exynos-ppmu";
768 reg = <0x13670000 0x2000>;
769 clocks = <&clock CLK_PPMUMFC_R>;
770 clock-names = "ppmu";
771 status = "disabled";
772 };
763 ppmu_dmc0: ppmu_dmc0@106a0000 {
764 compatible = "samsung,exynos-ppmu";
765 reg = <0x106a0000 0x2000>;
766 clocks = <&clock CLK_PPMUDMC0>;
767 clock-names = "ppmu";
768 status = "disabled";
769 };
770

--- 91 unchanged lines hidden (view full) ---

862
863 ppmu_mfc_right: ppmu_mfc_right@13670000 {
864 compatible = "samsung,exynos-ppmu";
865 reg = <0x13670000 0x2000>;
866 clocks = <&clock CLK_PPMUMFC_R>;
867 clock-names = "ppmu";
868 status = "disabled";
869 };
870
871 sysmmu_mfc_l: sysmmu@13620000 {
872 compatible = "samsung,exynos-sysmmu";
873 reg = <0x13620000 0x1000>;
874 interrupt-parent = <&combiner>;
875 interrupts = <5 5>;
876 clock-names = "sysmmu", "master";
877 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
878 power-domains = <&pd_mfc>;
879 #iommu-cells = <0>;
880 };
881
882 sysmmu_mfc_r: sysmmu@13630000 {
883 compatible = "samsung,exynos-sysmmu";
884 reg = <0x13630000 0x1000>;
885 interrupt-parent = <&combiner>;
886 interrupts = <5 6>;
887 clock-names = "sysmmu", "master";
888 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
889 power-domains = <&pd_mfc>;
890 #iommu-cells = <0>;
891 };
892
893 sysmmu_tv: sysmmu@12E20000 {
894 compatible = "samsung,exynos-sysmmu";
895 reg = <0x12E20000 0x1000>;
896 interrupt-parent = <&combiner>;
897 interrupts = <5 4>;
898 clock-names = "sysmmu", "master";
899 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
900 power-domains = <&pd_tv>;
901 #iommu-cells = <0>;
902 };
903
904 sysmmu_fimc0: sysmmu@11A20000 {
905 compatible = "samsung,exynos-sysmmu";
906 reg = <0x11A20000 0x1000>;
907 interrupt-parent = <&combiner>;
908 interrupts = <4 2>;
909 clock-names = "sysmmu", "master";
910 clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
911 power-domains = <&pd_cam>;
912 #iommu-cells = <0>;
913 };
914
915 sysmmu_fimc1: sysmmu@11A30000 {
916 compatible = "samsung,exynos-sysmmu";
917 reg = <0x11A30000 0x1000>;
918 interrupt-parent = <&combiner>;
919 interrupts = <4 3>;
920 clock-names = "sysmmu", "master";
921 clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
922 power-domains = <&pd_cam>;
923 #iommu-cells = <0>;
924 };
925
926 sysmmu_fimc2: sysmmu@11A40000 {
927 compatible = "samsung,exynos-sysmmu";
928 reg = <0x11A40000 0x1000>;
929 interrupt-parent = <&combiner>;
930 interrupts = <4 4>;
931 clock-names = "sysmmu", "master";
932 clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
933 power-domains = <&pd_cam>;
934 #iommu-cells = <0>;
935 };
936
937 sysmmu_fimc3: sysmmu@11A50000 {
938 compatible = "samsung,exynos-sysmmu";
939 reg = <0x11A50000 0x1000>;
940 interrupt-parent = <&combiner>;
941 interrupts = <4 5>;
942 clock-names = "sysmmu", "master";
943 clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
944 power-domains = <&pd_cam>;
945 #iommu-cells = <0>;
946 };
947
948 sysmmu_jpeg: sysmmu@11A60000 {
949 compatible = "samsung,exynos-sysmmu";
950 reg = <0x11A60000 0x1000>;
951 interrupt-parent = <&combiner>;
952 interrupts = <4 6>;
953 clock-names = "sysmmu", "master";
954 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
955 power-domains = <&pd_cam>;
956 #iommu-cells = <0>;
957 };
958
959 sysmmu_rotator: sysmmu@12A30000 {
960 compatible = "samsung,exynos-sysmmu";
961 reg = <0x12A30000 0x1000>;
962 interrupt-parent = <&combiner>;
963 interrupts = <5 0>;
964 clock-names = "sysmmu", "master";
965 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
966 #iommu-cells = <0>;
967 };
968
969 sysmmu_fimd0: sysmmu@11E20000 {
970 compatible = "samsung,exynos-sysmmu";
971 reg = <0x11E20000 0x1000>;
972 interrupt-parent = <&combiner>;
973 interrupts = <5 2>;
974 clock-names = "sysmmu", "master";
975 clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
976 power-domains = <&pd_lcd0>;
977 #iommu-cells = <0>;
978 };
979
980 prng: rng@10830400 {
981 compatible = "samsung,exynos4-rng";
982 reg = <0x10830400 0x200>;
983 clocks = <&clock CLK_SSS>;
984 clock-names = "secss";
985 status = "disabled";
986 };
773};
987};