1/* 2 * Samsung's Exynos4 SoC series common device tree source 3 * 4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * Copyright (c) 2010-2011 Linaro Ltd. 7 * www.linaro.org 8 * 9 * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular 10 * SoCs from Exynos4 series can include this file and provide values for SoCs 11 * specfic bindings. 12 * 13 * Note: This file does not include device nodes for all the controllers in 14 * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional 15 * nodes can be added to this file. 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License version 2 as 19 * published by the Free Software Foundation. 20 */ 21 22#include <dt-bindings/clock/exynos4.h> 23#include <dt-bindings/clock/exynos-audss-clk.h> 24#include "skeleton.dtsi" 25 26/ { 27 interrupt-parent = <&gic>; 28 29 aliases { 30 spi0 = &spi_0; 31 spi1 = &spi_1; 32 spi2 = &spi_2; 33 i2c0 = &i2c_0; 34 i2c1 = &i2c_1; 35 i2c2 = &i2c_2; 36 i2c3 = &i2c_3; 37 i2c4 = &i2c_4; 38 i2c5 = &i2c_5; 39 i2c6 = &i2c_6; 40 i2c7 = &i2c_7;
| 1/* 2 * Samsung's Exynos4 SoC series common device tree source 3 * 4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * Copyright (c) 2010-2011 Linaro Ltd. 7 * www.linaro.org 8 * 9 * Samsung's Exynos4 SoC series device nodes are listed in this file. Particular 10 * SoCs from Exynos4 series can include this file and provide values for SoCs 11 * specfic bindings. 12 * 13 * Note: This file does not include device nodes for all the controllers in 14 * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional 15 * nodes can be added to this file. 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License version 2 as 19 * published by the Free Software Foundation. 20 */ 21 22#include <dt-bindings/clock/exynos4.h> 23#include <dt-bindings/clock/exynos-audss-clk.h> 24#include "skeleton.dtsi" 25 26/ { 27 interrupt-parent = <&gic>; 28 29 aliases { 30 spi0 = &spi_0; 31 spi1 = &spi_1; 32 spi2 = &spi_2; 33 i2c0 = &i2c_0; 34 i2c1 = &i2c_1; 35 i2c2 = &i2c_2; 36 i2c3 = &i2c_3; 37 i2c4 = &i2c_4; 38 i2c5 = &i2c_5; 39 i2c6 = &i2c_6; 40 i2c7 = &i2c_7;
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| 41 i2c8 = &i2c_8;
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41 csis0 = &csis_0; 42 csis1 = &csis_1; 43 fimc0 = &fimc_0; 44 fimc1 = &fimc_1; 45 fimc2 = &fimc_2; 46 fimc3 = &fimc_3; 47 serial0 = &serial_0; 48 serial1 = &serial_1; 49 serial2 = &serial_2; 50 serial3 = &serial_3; 51 }; 52 53 clock_audss: clock-controller@03810000 { 54 compatible = "samsung,exynos4210-audss-clock"; 55 reg = <0x03810000 0x0C>; 56 #clock-cells = <1>; 57 }; 58 59 i2s0: i2s@03830000 { 60 compatible = "samsung,s5pv210-i2s"; 61 reg = <0x03830000 0x100>; 62 clocks = <&clock_audss EXYNOS_I2S_BUS>; 63 clock-names = "iis"; 64 #clock-cells = <1>; 65 clock-output-names = "i2s_cdclk0"; 66 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>; 67 dma-names = "tx", "rx", "tx-sec"; 68 samsung,idma-addr = <0x03000000>; 69 #sound-dai-cells = <1>; 70 status = "disabled"; 71 }; 72 73 chipid@10000000 { 74 compatible = "samsung,exynos4210-chipid"; 75 reg = <0x10000000 0x100>; 76 }; 77 78 mipi_phy: video-phy@10020710 { 79 compatible = "samsung,s5pv210-mipi-video-phy";
| 42 csis0 = &csis_0; 43 csis1 = &csis_1; 44 fimc0 = &fimc_0; 45 fimc1 = &fimc_1; 46 fimc2 = &fimc_2; 47 fimc3 = &fimc_3; 48 serial0 = &serial_0; 49 serial1 = &serial_1; 50 serial2 = &serial_2; 51 serial3 = &serial_3; 52 }; 53 54 clock_audss: clock-controller@03810000 { 55 compatible = "samsung,exynos4210-audss-clock"; 56 reg = <0x03810000 0x0C>; 57 #clock-cells = <1>; 58 }; 59 60 i2s0: i2s@03830000 { 61 compatible = "samsung,s5pv210-i2s"; 62 reg = <0x03830000 0x100>; 63 clocks = <&clock_audss EXYNOS_I2S_BUS>; 64 clock-names = "iis"; 65 #clock-cells = <1>; 66 clock-output-names = "i2s_cdclk0"; 67 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>; 68 dma-names = "tx", "rx", "tx-sec"; 69 samsung,idma-addr = <0x03000000>; 70 #sound-dai-cells = <1>; 71 status = "disabled"; 72 }; 73 74 chipid@10000000 { 75 compatible = "samsung,exynos4210-chipid"; 76 reg = <0x10000000 0x100>; 77 }; 78 79 mipi_phy: video-phy@10020710 { 80 compatible = "samsung,s5pv210-mipi-video-phy";
|
80 reg = <0x10020710 8>;
| |
81 #phy-cells = <1>; 82 syscon = <&pmu_system_controller>; 83 }; 84 85 pd_mfc: mfc-power-domain@10023C40 { 86 compatible = "samsung,exynos4210-pd"; 87 reg = <0x10023C40 0x20>; 88 #power-domain-cells = <0>; 89 }; 90 91 pd_g3d: g3d-power-domain@10023C60 { 92 compatible = "samsung,exynos4210-pd"; 93 reg = <0x10023C60 0x20>; 94 #power-domain-cells = <0>; 95 }; 96 97 pd_lcd0: lcd0-power-domain@10023C80 { 98 compatible = "samsung,exynos4210-pd"; 99 reg = <0x10023C80 0x20>; 100 #power-domain-cells = <0>; 101 }; 102 103 pd_tv: tv-power-domain@10023C20 { 104 compatible = "samsung,exynos4210-pd"; 105 reg = <0x10023C20 0x20>; 106 #power-domain-cells = <0>;
| 81 #phy-cells = <1>; 82 syscon = <&pmu_system_controller>; 83 }; 84 85 pd_mfc: mfc-power-domain@10023C40 { 86 compatible = "samsung,exynos4210-pd"; 87 reg = <0x10023C40 0x20>; 88 #power-domain-cells = <0>; 89 }; 90 91 pd_g3d: g3d-power-domain@10023C60 { 92 compatible = "samsung,exynos4210-pd"; 93 reg = <0x10023C60 0x20>; 94 #power-domain-cells = <0>; 95 }; 96 97 pd_lcd0: lcd0-power-domain@10023C80 { 98 compatible = "samsung,exynos4210-pd"; 99 reg = <0x10023C80 0x20>; 100 #power-domain-cells = <0>; 101 }; 102 103 pd_tv: tv-power-domain@10023C20 { 104 compatible = "samsung,exynos4210-pd"; 105 reg = <0x10023C20 0x20>; 106 #power-domain-cells = <0>;
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| 107 power-domains = <&pd_lcd0>;
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107 }; 108 109 pd_cam: cam-power-domain@10023C00 { 110 compatible = "samsung,exynos4210-pd"; 111 reg = <0x10023C00 0x20>; 112 #power-domain-cells = <0>; 113 }; 114 115 pd_gps: gps-power-domain@10023CE0 { 116 compatible = "samsung,exynos4210-pd"; 117 reg = <0x10023CE0 0x20>; 118 #power-domain-cells = <0>; 119 }; 120 121 pd_gps_alive: gps-alive-power-domain@10023D00 { 122 compatible = "samsung,exynos4210-pd"; 123 reg = <0x10023D00 0x20>; 124 #power-domain-cells = <0>; 125 }; 126 127 gic: interrupt-controller@10490000 { 128 compatible = "arm,cortex-a9-gic"; 129 #interrupt-cells = <3>; 130 interrupt-controller; 131 reg = <0x10490000 0x10000>, <0x10480000 0x10000>; 132 }; 133 134 combiner: interrupt-controller@10440000 { 135 compatible = "samsung,exynos4210-combiner"; 136 #interrupt-cells = <2>; 137 interrupt-controller; 138 reg = <0x10440000 0x1000>; 139 }; 140 141 pmu { 142 compatible = "arm,cortex-a9-pmu"; 143 interrupt-parent = <&combiner>; 144 interrupts = <2 2>, <3 2>; 145 }; 146 147 sys_reg: syscon@10010000 { 148 compatible = "samsung,exynos4-sysreg", "syscon"; 149 reg = <0x10010000 0x400>; 150 }; 151 152 pmu_system_controller: system-controller@10020000 { 153 compatible = "samsung,exynos4210-pmu", "syscon"; 154 reg = <0x10020000 0x4000>;
| 108 }; 109 110 pd_cam: cam-power-domain@10023C00 { 111 compatible = "samsung,exynos4210-pd"; 112 reg = <0x10023C00 0x20>; 113 #power-domain-cells = <0>; 114 }; 115 116 pd_gps: gps-power-domain@10023CE0 { 117 compatible = "samsung,exynos4210-pd"; 118 reg = <0x10023CE0 0x20>; 119 #power-domain-cells = <0>; 120 }; 121 122 pd_gps_alive: gps-alive-power-domain@10023D00 { 123 compatible = "samsung,exynos4210-pd"; 124 reg = <0x10023D00 0x20>; 125 #power-domain-cells = <0>; 126 }; 127 128 gic: interrupt-controller@10490000 { 129 compatible = "arm,cortex-a9-gic"; 130 #interrupt-cells = <3>; 131 interrupt-controller; 132 reg = <0x10490000 0x10000>, <0x10480000 0x10000>; 133 }; 134 135 combiner: interrupt-controller@10440000 { 136 compatible = "samsung,exynos4210-combiner"; 137 #interrupt-cells = <2>; 138 interrupt-controller; 139 reg = <0x10440000 0x1000>; 140 }; 141 142 pmu { 143 compatible = "arm,cortex-a9-pmu"; 144 interrupt-parent = <&combiner>; 145 interrupts = <2 2>, <3 2>; 146 }; 147 148 sys_reg: syscon@10010000 { 149 compatible = "samsung,exynos4-sysreg", "syscon"; 150 reg = <0x10010000 0x400>; 151 }; 152 153 pmu_system_controller: system-controller@10020000 { 154 compatible = "samsung,exynos4210-pmu", "syscon"; 155 reg = <0x10020000 0x4000>;
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| 156 interrupt-controller; 157 #interrupt-cells = <3>; 158 interrupt-parent = <&gic>;
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155 }; 156
| 159 }; 160
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| 161 poweroff: syscon-poweroff { 162 compatible = "syscon-poweroff"; 163 regmap = <&pmu_system_controller>; 164 offset = <0x330C>; /* PS_HOLD_CONTROL */ 165 mask = <0x5200>; /* reset value */ 166 }; 167 168 reboot: syscon-reboot { 169 compatible = "syscon-reboot"; 170 regmap = <&pmu_system_controller>; 171 offset = <0x0400>; /* SWRESET */ 172 mask = <0x1>; 173 }; 174
|
157 dsi_0: dsi@11C80000 { 158 compatible = "samsung,exynos4210-mipi-dsi"; 159 reg = <0x11C80000 0x10000>; 160 interrupts = <0 79 0>; 161 power-domains = <&pd_lcd0>; 162 phys = <&mipi_phy 1>; 163 phy-names = "dsim"; 164 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
| 175 dsi_0: dsi@11C80000 { 176 compatible = "samsung,exynos4210-mipi-dsi"; 177 reg = <0x11C80000 0x10000>; 178 interrupts = <0 79 0>; 179 power-domains = <&pd_lcd0>; 180 phys = <&mipi_phy 1>; 181 phy-names = "dsim"; 182 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
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165 clock-names = "bus_clk", "pll_clk";
| 183 clock-names = "bus_clk", "sclk_mipi";
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166 status = "disabled"; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 }; 170 171 camera { 172 compatible = "samsung,fimc", "simple-bus"; 173 status = "disabled"; 174 #address-cells = <1>; 175 #size-cells = <1>; 176 #clock-cells = <1>; 177 clock-output-names = "cam_a_clkout", "cam_b_clkout"; 178 ranges; 179 180 fimc_0: fimc@11800000 { 181 compatible = "samsung,exynos4210-fimc"; 182 reg = <0x11800000 0x1000>; 183 interrupts = <0 84 0>; 184 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>; 185 clock-names = "fimc", "sclk_fimc"; 186 power-domains = <&pd_cam>; 187 samsung,sysreg = <&sys_reg>;
| 184 status = "disabled"; 185 #address-cells = <1>; 186 #size-cells = <0>; 187 }; 188 189 camera { 190 compatible = "samsung,fimc", "simple-bus"; 191 status = "disabled"; 192 #address-cells = <1>; 193 #size-cells = <1>; 194 #clock-cells = <1>; 195 clock-output-names = "cam_a_clkout", "cam_b_clkout"; 196 ranges; 197 198 fimc_0: fimc@11800000 { 199 compatible = "samsung,exynos4210-fimc"; 200 reg = <0x11800000 0x1000>; 201 interrupts = <0 84 0>; 202 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>; 203 clock-names = "fimc", "sclk_fimc"; 204 power-domains = <&pd_cam>; 205 samsung,sysreg = <&sys_reg>;
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| 206 iommus = <&sysmmu_fimc0>;
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188 status = "disabled"; 189 }; 190 191 fimc_1: fimc@11810000 { 192 compatible = "samsung,exynos4210-fimc"; 193 reg = <0x11810000 0x1000>; 194 interrupts = <0 85 0>; 195 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>; 196 clock-names = "fimc", "sclk_fimc"; 197 power-domains = <&pd_cam>; 198 samsung,sysreg = <&sys_reg>;
| 207 status = "disabled"; 208 }; 209 210 fimc_1: fimc@11810000 { 211 compatible = "samsung,exynos4210-fimc"; 212 reg = <0x11810000 0x1000>; 213 interrupts = <0 85 0>; 214 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>; 215 clock-names = "fimc", "sclk_fimc"; 216 power-domains = <&pd_cam>; 217 samsung,sysreg = <&sys_reg>;
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| 218 iommus = <&sysmmu_fimc1>;
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199 status = "disabled"; 200 }; 201 202 fimc_2: fimc@11820000 { 203 compatible = "samsung,exynos4210-fimc"; 204 reg = <0x11820000 0x1000>; 205 interrupts = <0 86 0>; 206 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>; 207 clock-names = "fimc", "sclk_fimc"; 208 power-domains = <&pd_cam>; 209 samsung,sysreg = <&sys_reg>;
| 219 status = "disabled"; 220 }; 221 222 fimc_2: fimc@11820000 { 223 compatible = "samsung,exynos4210-fimc"; 224 reg = <0x11820000 0x1000>; 225 interrupts = <0 86 0>; 226 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>; 227 clock-names = "fimc", "sclk_fimc"; 228 power-domains = <&pd_cam>; 229 samsung,sysreg = <&sys_reg>;
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| 230 iommus = <&sysmmu_fimc2>;
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210 status = "disabled"; 211 }; 212 213 fimc_3: fimc@11830000 { 214 compatible = "samsung,exynos4210-fimc"; 215 reg = <0x11830000 0x1000>; 216 interrupts = <0 87 0>; 217 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>; 218 clock-names = "fimc", "sclk_fimc"; 219 power-domains = <&pd_cam>; 220 samsung,sysreg = <&sys_reg>;
| 231 status = "disabled"; 232 }; 233 234 fimc_3: fimc@11830000 { 235 compatible = "samsung,exynos4210-fimc"; 236 reg = <0x11830000 0x1000>; 237 interrupts = <0 87 0>; 238 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>; 239 clock-names = "fimc", "sclk_fimc"; 240 power-domains = <&pd_cam>; 241 samsung,sysreg = <&sys_reg>;
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| 242 iommus = <&sysmmu_fimc3>;
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221 status = "disabled"; 222 }; 223 224 csis_0: csis@11880000 { 225 compatible = "samsung,exynos4210-csis"; 226 reg = <0x11880000 0x4000>; 227 interrupts = <0 78 0>; 228 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>; 229 clock-names = "csis", "sclk_csis"; 230 bus-width = <4>; 231 power-domains = <&pd_cam>; 232 phys = <&mipi_phy 0>; 233 phy-names = "csis"; 234 status = "disabled"; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 }; 238 239 csis_1: csis@11890000 { 240 compatible = "samsung,exynos4210-csis"; 241 reg = <0x11890000 0x4000>; 242 interrupts = <0 80 0>; 243 clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>; 244 clock-names = "csis", "sclk_csis"; 245 bus-width = <2>; 246 power-domains = <&pd_cam>; 247 phys = <&mipi_phy 2>; 248 phy-names = "csis"; 249 status = "disabled"; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 }; 253 }; 254
| 243 status = "disabled"; 244 }; 245 246 csis_0: csis@11880000 { 247 compatible = "samsung,exynos4210-csis"; 248 reg = <0x11880000 0x4000>; 249 interrupts = <0 78 0>; 250 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>; 251 clock-names = "csis", "sclk_csis"; 252 bus-width = <4>; 253 power-domains = <&pd_cam>; 254 phys = <&mipi_phy 0>; 255 phy-names = "csis"; 256 status = "disabled"; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 }; 260 261 csis_1: csis@11890000 { 262 compatible = "samsung,exynos4210-csis"; 263 reg = <0x11890000 0x4000>; 264 interrupts = <0 80 0>; 265 clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>; 266 clock-names = "csis", "sclk_csis"; 267 bus-width = <2>; 268 power-domains = <&pd_cam>; 269 phys = <&mipi_phy 2>; 270 phy-names = "csis"; 271 status = "disabled"; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 }; 275 }; 276
|
255 watchdog@10060000 {
| 277 watchdog: watchdog@10060000 {
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256 compatible = "samsung,s3c2410-wdt"; 257 reg = <0x10060000 0x100>; 258 interrupts = <0 43 0>; 259 clocks = <&clock CLK_WDT>; 260 clock-names = "watchdog"; 261 status = "disabled"; 262 }; 263
| 278 compatible = "samsung,s3c2410-wdt"; 279 reg = <0x10060000 0x100>; 280 interrupts = <0 43 0>; 281 clocks = <&clock CLK_WDT>; 282 clock-names = "watchdog"; 283 status = "disabled"; 284 }; 285
|
264 rtc@10070000 {
| 286 rtc: rtc@10070000 {
|
265 compatible = "samsung,s3c6410-rtc"; 266 reg = <0x10070000 0x100>;
| 287 compatible = "samsung,s3c6410-rtc"; 288 reg = <0x10070000 0x100>;
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| 289 interrupt-parent = <&pmu_system_controller>;
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267 interrupts = <0 44 0>, <0 45 0>; 268 clocks = <&clock CLK_RTC>; 269 clock-names = "rtc"; 270 status = "disabled"; 271 }; 272
| 290 interrupts = <0 44 0>, <0 45 0>; 291 clocks = <&clock CLK_RTC>; 292 clock-names = "rtc"; 293 status = "disabled"; 294 }; 295
|
273 keypad@100A0000 {
| 296 keypad: keypad@100A0000 {
|
274 compatible = "samsung,s5pv210-keypad"; 275 reg = <0x100A0000 0x100>; 276 interrupts = <0 109 0>; 277 clocks = <&clock CLK_KEYIF>; 278 clock-names = "keypad"; 279 status = "disabled"; 280 }; 281
| 297 compatible = "samsung,s5pv210-keypad"; 298 reg = <0x100A0000 0x100>; 299 interrupts = <0 109 0>; 300 clocks = <&clock CLK_KEYIF>; 301 clock-names = "keypad"; 302 status = "disabled"; 303 }; 304
|
282 sdhci@12510000 {
| 305 sdhci_0: sdhci@12510000 {
|
283 compatible = "samsung,exynos4210-sdhci"; 284 reg = <0x12510000 0x100>; 285 interrupts = <0 73 0>; 286 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; 287 clock-names = "hsmmc", "mmc_busclk.2"; 288 status = "disabled"; 289 }; 290
| 306 compatible = "samsung,exynos4210-sdhci"; 307 reg = <0x12510000 0x100>; 308 interrupts = <0 73 0>; 309 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>; 310 clock-names = "hsmmc", "mmc_busclk.2"; 311 status = "disabled"; 312 }; 313
|
291 sdhci@12520000 {
| 314 sdhci_1: sdhci@12520000 {
|
292 compatible = "samsung,exynos4210-sdhci"; 293 reg = <0x12520000 0x100>; 294 interrupts = <0 74 0>; 295 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; 296 clock-names = "hsmmc", "mmc_busclk.2"; 297 status = "disabled"; 298 }; 299
| 315 compatible = "samsung,exynos4210-sdhci"; 316 reg = <0x12520000 0x100>; 317 interrupts = <0 74 0>; 318 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>; 319 clock-names = "hsmmc", "mmc_busclk.2"; 320 status = "disabled"; 321 }; 322
|
300 sdhci@12530000 {
| 323 sdhci_2: sdhci@12530000 {
|
301 compatible = "samsung,exynos4210-sdhci"; 302 reg = <0x12530000 0x100>; 303 interrupts = <0 75 0>; 304 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; 305 clock-names = "hsmmc", "mmc_busclk.2"; 306 status = "disabled"; 307 }; 308
| 324 compatible = "samsung,exynos4210-sdhci"; 325 reg = <0x12530000 0x100>; 326 interrupts = <0 75 0>; 327 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>; 328 clock-names = "hsmmc", "mmc_busclk.2"; 329 status = "disabled"; 330 }; 331
|
309 sdhci@12540000 {
| 332 sdhci_3: sdhci@12540000 {
|
310 compatible = "samsung,exynos4210-sdhci"; 311 reg = <0x12540000 0x100>; 312 interrupts = <0 76 0>; 313 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; 314 clock-names = "hsmmc", "mmc_busclk.2"; 315 status = "disabled"; 316 }; 317 318 exynos_usbphy: exynos-usbphy@125B0000 { 319 compatible = "samsung,exynos4210-usb2-phy"; 320 reg = <0x125B0000 0x100>; 321 samsung,pmureg-phandle = <&pmu_system_controller>; 322 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; 323 clock-names = "phy", "ref"; 324 #phy-cells = <1>; 325 status = "disabled"; 326 }; 327
| 333 compatible = "samsung,exynos4210-sdhci"; 334 reg = <0x12540000 0x100>; 335 interrupts = <0 76 0>; 336 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>; 337 clock-names = "hsmmc", "mmc_busclk.2"; 338 status = "disabled"; 339 }; 340 341 exynos_usbphy: exynos-usbphy@125B0000 { 342 compatible = "samsung,exynos4210-usb2-phy"; 343 reg = <0x125B0000 0x100>; 344 samsung,pmureg-phandle = <&pmu_system_controller>; 345 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; 346 clock-names = "phy", "ref"; 347 #phy-cells = <1>; 348 status = "disabled"; 349 }; 350
|
328 hsotg@12480000 {
| 351 hsotg: hsotg@12480000 {
|
329 compatible = "samsung,s3c6400-hsotg"; 330 reg = <0x12480000 0x20000>; 331 interrupts = <0 71 0>; 332 clocks = <&clock CLK_USB_DEVICE>; 333 clock-names = "otg"; 334 phys = <&exynos_usbphy 0>; 335 phy-names = "usb2-phy"; 336 status = "disabled"; 337 }; 338
| 352 compatible = "samsung,s3c6400-hsotg"; 353 reg = <0x12480000 0x20000>; 354 interrupts = <0 71 0>; 355 clocks = <&clock CLK_USB_DEVICE>; 356 clock-names = "otg"; 357 phys = <&exynos_usbphy 0>; 358 phy-names = "usb2-phy"; 359 status = "disabled"; 360 }; 361
|
339 ehci@12580000 {
| 362 ehci: ehci@12580000 {
|
340 compatible = "samsung,exynos4210-ehci"; 341 reg = <0x12580000 0x100>; 342 interrupts = <0 70 0>; 343 clocks = <&clock CLK_USB_HOST>; 344 clock-names = "usbhost"; 345 status = "disabled"; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 port@0 { 349 reg = <0>; 350 phys = <&exynos_usbphy 1>; 351 status = "disabled"; 352 }; 353 port@1 { 354 reg = <1>; 355 phys = <&exynos_usbphy 2>; 356 status = "disabled"; 357 }; 358 port@2 { 359 reg = <2>; 360 phys = <&exynos_usbphy 3>; 361 status = "disabled"; 362 }; 363 }; 364
| 363 compatible = "samsung,exynos4210-ehci"; 364 reg = <0x12580000 0x100>; 365 interrupts = <0 70 0>; 366 clocks = <&clock CLK_USB_HOST>; 367 clock-names = "usbhost"; 368 status = "disabled"; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 port@0 { 372 reg = <0>; 373 phys = <&exynos_usbphy 1>; 374 status = "disabled"; 375 }; 376 port@1 { 377 reg = <1>; 378 phys = <&exynos_usbphy 2>; 379 status = "disabled"; 380 }; 381 port@2 { 382 reg = <2>; 383 phys = <&exynos_usbphy 3>; 384 status = "disabled"; 385 }; 386 }; 387
|
365 ohci@12590000 {
| 388 ohci: ohci@12590000 {
|
366 compatible = "samsung,exynos4210-ohci"; 367 reg = <0x12590000 0x100>; 368 interrupts = <0 70 0>; 369 clocks = <&clock CLK_USB_HOST>; 370 clock-names = "usbhost"; 371 status = "disabled"; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 port@0 { 375 reg = <0>; 376 phys = <&exynos_usbphy 1>; 377 status = "disabled"; 378 }; 379 }; 380 381 i2s1: i2s@13960000 { 382 compatible = "samsung,s3c6410-i2s"; 383 reg = <0x13960000 0x100>; 384 clocks = <&clock CLK_I2S1>; 385 clock-names = "iis"; 386 #clock-cells = <1>; 387 clock-output-names = "i2s_cdclk1"; 388 dmas = <&pdma1 12>, <&pdma1 11>; 389 dma-names = "tx", "rx"; 390 #sound-dai-cells = <1>; 391 status = "disabled"; 392 }; 393 394 i2s2: i2s@13970000 { 395 compatible = "samsung,s3c6410-i2s"; 396 reg = <0x13970000 0x100>; 397 clocks = <&clock CLK_I2S2>; 398 clock-names = "iis"; 399 #clock-cells = <1>; 400 clock-output-names = "i2s_cdclk2"; 401 dmas = <&pdma0 14>, <&pdma0 13>; 402 dma-names = "tx", "rx"; 403 #sound-dai-cells = <1>; 404 status = "disabled"; 405 }; 406 407 mfc: codec@13400000 { 408 compatible = "samsung,mfc-v5"; 409 reg = <0x13400000 0x10000>; 410 interrupts = <0 94 0>; 411 power-domains = <&pd_mfc>; 412 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; 413 clock-names = "mfc", "sclk_mfc";
| 389 compatible = "samsung,exynos4210-ohci"; 390 reg = <0x12590000 0x100>; 391 interrupts = <0 70 0>; 392 clocks = <&clock CLK_USB_HOST>; 393 clock-names = "usbhost"; 394 status = "disabled"; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 port@0 { 398 reg = <0>; 399 phys = <&exynos_usbphy 1>; 400 status = "disabled"; 401 }; 402 }; 403 404 i2s1: i2s@13960000 { 405 compatible = "samsung,s3c6410-i2s"; 406 reg = <0x13960000 0x100>; 407 clocks = <&clock CLK_I2S1>; 408 clock-names = "iis"; 409 #clock-cells = <1>; 410 clock-output-names = "i2s_cdclk1"; 411 dmas = <&pdma1 12>, <&pdma1 11>; 412 dma-names = "tx", "rx"; 413 #sound-dai-cells = <1>; 414 status = "disabled"; 415 }; 416 417 i2s2: i2s@13970000 { 418 compatible = "samsung,s3c6410-i2s"; 419 reg = <0x13970000 0x100>; 420 clocks = <&clock CLK_I2S2>; 421 clock-names = "iis"; 422 #clock-cells = <1>; 423 clock-output-names = "i2s_cdclk2"; 424 dmas = <&pdma0 14>, <&pdma0 13>; 425 dma-names = "tx", "rx"; 426 #sound-dai-cells = <1>; 427 status = "disabled"; 428 }; 429 430 mfc: codec@13400000 { 431 compatible = "samsung,mfc-v5"; 432 reg = <0x13400000 0x10000>; 433 interrupts = <0 94 0>; 434 power-domains = <&pd_mfc>; 435 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; 436 clock-names = "mfc", "sclk_mfc";
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| 437 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>; 438 iommu-names = "left", "right";
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414 status = "disabled"; 415 }; 416 417 serial_0: serial@13800000 { 418 compatible = "samsung,exynos4210-uart"; 419 reg = <0x13800000 0x100>; 420 interrupts = <0 52 0>; 421 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 422 clock-names = "uart", "clk_uart_baud0";
| 439 status = "disabled"; 440 }; 441 442 serial_0: serial@13800000 { 443 compatible = "samsung,exynos4210-uart"; 444 reg = <0x13800000 0x100>; 445 interrupts = <0 52 0>; 446 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; 447 clock-names = "uart", "clk_uart_baud0";
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| 448 dmas = <&pdma0 15>, <&pdma0 16>; 449 dma-names = "rx", "tx";
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423 status = "disabled"; 424 }; 425 426 serial_1: serial@13810000 { 427 compatible = "samsung,exynos4210-uart"; 428 reg = <0x13810000 0x100>; 429 interrupts = <0 53 0>; 430 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 431 clock-names = "uart", "clk_uart_baud0";
| 450 status = "disabled"; 451 }; 452 453 serial_1: serial@13810000 { 454 compatible = "samsung,exynos4210-uart"; 455 reg = <0x13810000 0x100>; 456 interrupts = <0 53 0>; 457 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; 458 clock-names = "uart", "clk_uart_baud0";
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| 459 dmas = <&pdma1 15>, <&pdma1 16>; 460 dma-names = "rx", "tx";
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432 status = "disabled"; 433 }; 434 435 serial_2: serial@13820000 { 436 compatible = "samsung,exynos4210-uart"; 437 reg = <0x13820000 0x100>; 438 interrupts = <0 54 0>; 439 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 440 clock-names = "uart", "clk_uart_baud0";
| 461 status = "disabled"; 462 }; 463 464 serial_2: serial@13820000 { 465 compatible = "samsung,exynos4210-uart"; 466 reg = <0x13820000 0x100>; 467 interrupts = <0 54 0>; 468 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 469 clock-names = "uart", "clk_uart_baud0";
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| 470 dmas = <&pdma0 17>, <&pdma0 18>; 471 dma-names = "rx", "tx";
|
441 status = "disabled"; 442 }; 443 444 serial_3: serial@13830000 { 445 compatible = "samsung,exynos4210-uart"; 446 reg = <0x13830000 0x100>; 447 interrupts = <0 55 0>; 448 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 449 clock-names = "uart", "clk_uart_baud0";
| 472 status = "disabled"; 473 }; 474 475 serial_3: serial@13830000 { 476 compatible = "samsung,exynos4210-uart"; 477 reg = <0x13830000 0x100>; 478 interrupts = <0 55 0>; 479 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>; 480 clock-names = "uart", "clk_uart_baud0";
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| 481 dmas = <&pdma1 17>, <&pdma1 18>; 482 dma-names = "rx", "tx";
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450 status = "disabled"; 451 }; 452 453 i2c_0: i2c@13860000 { 454 #address-cells = <1>; 455 #size-cells = <0>; 456 compatible = "samsung,s3c2440-i2c"; 457 reg = <0x13860000 0x100>; 458 interrupts = <0 58 0>; 459 clocks = <&clock CLK_I2C0>; 460 clock-names = "i2c"; 461 pinctrl-names = "default"; 462 pinctrl-0 = <&i2c0_bus>; 463 status = "disabled"; 464 }; 465 466 i2c_1: i2c@13870000 { 467 #address-cells = <1>; 468 #size-cells = <0>; 469 compatible = "samsung,s3c2440-i2c"; 470 reg = <0x13870000 0x100>; 471 interrupts = <0 59 0>; 472 clocks = <&clock CLK_I2C1>; 473 clock-names = "i2c"; 474 pinctrl-names = "default"; 475 pinctrl-0 = <&i2c1_bus>; 476 status = "disabled"; 477 }; 478 479 i2c_2: i2c@13880000 { 480 #address-cells = <1>; 481 #size-cells = <0>; 482 compatible = "samsung,s3c2440-i2c"; 483 reg = <0x13880000 0x100>; 484 interrupts = <0 60 0>; 485 clocks = <&clock CLK_I2C2>; 486 clock-names = "i2c"; 487 pinctrl-names = "default"; 488 pinctrl-0 = <&i2c2_bus>; 489 status = "disabled"; 490 }; 491 492 i2c_3: i2c@13890000 { 493 #address-cells = <1>; 494 #size-cells = <0>; 495 compatible = "samsung,s3c2440-i2c"; 496 reg = <0x13890000 0x100>; 497 interrupts = <0 61 0>; 498 clocks = <&clock CLK_I2C3>; 499 clock-names = "i2c"; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&i2c3_bus>; 502 status = "disabled"; 503 }; 504 505 i2c_4: i2c@138A0000 { 506 #address-cells = <1>; 507 #size-cells = <0>; 508 compatible = "samsung,s3c2440-i2c"; 509 reg = <0x138A0000 0x100>; 510 interrupts = <0 62 0>; 511 clocks = <&clock CLK_I2C4>; 512 clock-names = "i2c"; 513 pinctrl-names = "default"; 514 pinctrl-0 = <&i2c4_bus>; 515 status = "disabled"; 516 }; 517 518 i2c_5: i2c@138B0000 { 519 #address-cells = <1>; 520 #size-cells = <0>; 521 compatible = "samsung,s3c2440-i2c"; 522 reg = <0x138B0000 0x100>; 523 interrupts = <0 63 0>; 524 clocks = <&clock CLK_I2C5>; 525 clock-names = "i2c"; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&i2c5_bus>; 528 status = "disabled"; 529 }; 530 531 i2c_6: i2c@138C0000 { 532 #address-cells = <1>; 533 #size-cells = <0>; 534 compatible = "samsung,s3c2440-i2c"; 535 reg = <0x138C0000 0x100>; 536 interrupts = <0 64 0>; 537 clocks = <&clock CLK_I2C6>; 538 clock-names = "i2c"; 539 pinctrl-names = "default"; 540 pinctrl-0 = <&i2c6_bus>; 541 status = "disabled"; 542 }; 543 544 i2c_7: i2c@138D0000 { 545 #address-cells = <1>; 546 #size-cells = <0>; 547 compatible = "samsung,s3c2440-i2c"; 548 reg = <0x138D0000 0x100>; 549 interrupts = <0 65 0>; 550 clocks = <&clock CLK_I2C7>; 551 clock-names = "i2c"; 552 pinctrl-names = "default"; 553 pinctrl-0 = <&i2c7_bus>; 554 status = "disabled"; 555 }; 556
| 483 status = "disabled"; 484 }; 485 486 i2c_0: i2c@13860000 { 487 #address-cells = <1>; 488 #size-cells = <0>; 489 compatible = "samsung,s3c2440-i2c"; 490 reg = <0x13860000 0x100>; 491 interrupts = <0 58 0>; 492 clocks = <&clock CLK_I2C0>; 493 clock-names = "i2c"; 494 pinctrl-names = "default"; 495 pinctrl-0 = <&i2c0_bus>; 496 status = "disabled"; 497 }; 498 499 i2c_1: i2c@13870000 { 500 #address-cells = <1>; 501 #size-cells = <0>; 502 compatible = "samsung,s3c2440-i2c"; 503 reg = <0x13870000 0x100>; 504 interrupts = <0 59 0>; 505 clocks = <&clock CLK_I2C1>; 506 clock-names = "i2c"; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&i2c1_bus>; 509 status = "disabled"; 510 }; 511 512 i2c_2: i2c@13880000 { 513 #address-cells = <1>; 514 #size-cells = <0>; 515 compatible = "samsung,s3c2440-i2c"; 516 reg = <0x13880000 0x100>; 517 interrupts = <0 60 0>; 518 clocks = <&clock CLK_I2C2>; 519 clock-names = "i2c"; 520 pinctrl-names = "default"; 521 pinctrl-0 = <&i2c2_bus>; 522 status = "disabled"; 523 }; 524 525 i2c_3: i2c@13890000 { 526 #address-cells = <1>; 527 #size-cells = <0>; 528 compatible = "samsung,s3c2440-i2c"; 529 reg = <0x13890000 0x100>; 530 interrupts = <0 61 0>; 531 clocks = <&clock CLK_I2C3>; 532 clock-names = "i2c"; 533 pinctrl-names = "default"; 534 pinctrl-0 = <&i2c3_bus>; 535 status = "disabled"; 536 }; 537 538 i2c_4: i2c@138A0000 { 539 #address-cells = <1>; 540 #size-cells = <0>; 541 compatible = "samsung,s3c2440-i2c"; 542 reg = <0x138A0000 0x100>; 543 interrupts = <0 62 0>; 544 clocks = <&clock CLK_I2C4>; 545 clock-names = "i2c"; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&i2c4_bus>; 548 status = "disabled"; 549 }; 550 551 i2c_5: i2c@138B0000 { 552 #address-cells = <1>; 553 #size-cells = <0>; 554 compatible = "samsung,s3c2440-i2c"; 555 reg = <0x138B0000 0x100>; 556 interrupts = <0 63 0>; 557 clocks = <&clock CLK_I2C5>; 558 clock-names = "i2c"; 559 pinctrl-names = "default"; 560 pinctrl-0 = <&i2c5_bus>; 561 status = "disabled"; 562 }; 563 564 i2c_6: i2c@138C0000 { 565 #address-cells = <1>; 566 #size-cells = <0>; 567 compatible = "samsung,s3c2440-i2c"; 568 reg = <0x138C0000 0x100>; 569 interrupts = <0 64 0>; 570 clocks = <&clock CLK_I2C6>; 571 clock-names = "i2c"; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&i2c6_bus>; 574 status = "disabled"; 575 }; 576 577 i2c_7: i2c@138D0000 { 578 #address-cells = <1>; 579 #size-cells = <0>; 580 compatible = "samsung,s3c2440-i2c"; 581 reg = <0x138D0000 0x100>; 582 interrupts = <0 65 0>; 583 clocks = <&clock CLK_I2C7>; 584 clock-names = "i2c"; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&i2c7_bus>; 587 status = "disabled"; 588 }; 589
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| 590 i2c_8: i2c@138E0000 { 591 #address-cells = <1>; 592 #size-cells = <0>; 593 compatible = "samsung,s3c2440-hdmiphy-i2c"; 594 reg = <0x138E0000 0x100>; 595 interrupts = <0 93 0>; 596 clocks = <&clock CLK_I2C_HDMI>; 597 clock-names = "i2c"; 598 status = "disabled"; 599 600 hdmi_i2c_phy: hdmiphy@38 { 601 compatible = "exynos4210-hdmiphy"; 602 reg = <0x38>; 603 }; 604 }; 605
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557 spi_0: spi@13920000 { 558 compatible = "samsung,exynos4210-spi"; 559 reg = <0x13920000 0x100>; 560 interrupts = <0 66 0>; 561 dmas = <&pdma0 7>, <&pdma0 6>; 562 dma-names = "tx", "rx"; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; 566 clock-names = "spi", "spi_busclk0"; 567 pinctrl-names = "default"; 568 pinctrl-0 = <&spi0_bus>; 569 status = "disabled"; 570 }; 571 572 spi_1: spi@13930000 { 573 compatible = "samsung,exynos4210-spi"; 574 reg = <0x13930000 0x100>; 575 interrupts = <0 67 0>; 576 dmas = <&pdma1 7>, <&pdma1 6>; 577 dma-names = "tx", "rx"; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; 581 clock-names = "spi", "spi_busclk0"; 582 pinctrl-names = "default"; 583 pinctrl-0 = <&spi1_bus>; 584 status = "disabled"; 585 }; 586 587 spi_2: spi@13940000 { 588 compatible = "samsung,exynos4210-spi"; 589 reg = <0x13940000 0x100>; 590 interrupts = <0 68 0>; 591 dmas = <&pdma0 9>, <&pdma0 8>; 592 dma-names = "tx", "rx"; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; 596 clock-names = "spi", "spi_busclk0"; 597 pinctrl-names = "default"; 598 pinctrl-0 = <&spi2_bus>; 599 status = "disabled"; 600 }; 601
| 606 spi_0: spi@13920000 { 607 compatible = "samsung,exynos4210-spi"; 608 reg = <0x13920000 0x100>; 609 interrupts = <0 66 0>; 610 dmas = <&pdma0 7>, <&pdma0 6>; 611 dma-names = "tx", "rx"; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>; 615 clock-names = "spi", "spi_busclk0"; 616 pinctrl-names = "default"; 617 pinctrl-0 = <&spi0_bus>; 618 status = "disabled"; 619 }; 620 621 spi_1: spi@13930000 { 622 compatible = "samsung,exynos4210-spi"; 623 reg = <0x13930000 0x100>; 624 interrupts = <0 67 0>; 625 dmas = <&pdma1 7>, <&pdma1 6>; 626 dma-names = "tx", "rx"; 627 #address-cells = <1>; 628 #size-cells = <0>; 629 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>; 630 clock-names = "spi", "spi_busclk0"; 631 pinctrl-names = "default"; 632 pinctrl-0 = <&spi1_bus>; 633 status = "disabled"; 634 }; 635 636 spi_2: spi@13940000 { 637 compatible = "samsung,exynos4210-spi"; 638 reg = <0x13940000 0x100>; 639 interrupts = <0 68 0>; 640 dmas = <&pdma0 9>, <&pdma0 8>; 641 dma-names = "tx", "rx"; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>; 645 clock-names = "spi", "spi_busclk0"; 646 pinctrl-names = "default"; 647 pinctrl-0 = <&spi2_bus>; 648 status = "disabled"; 649 }; 650
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602 pwm@139D0000 {
| 651 pwm: pwm@139D0000 {
|
603 compatible = "samsung,exynos4210-pwm"; 604 reg = <0x139D0000 0x1000>; 605 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>; 606 clocks = <&clock CLK_PWM>; 607 clock-names = "timers"; 608 #pwm-cells = <3>; 609 status = "disabled"; 610 }; 611 612 amba { 613 #address-cells = <1>; 614 #size-cells = <1>; 615 compatible = "arm,amba-bus"; 616 interrupt-parent = <&gic>; 617 ranges; 618 619 pdma0: pdma@12680000 { 620 compatible = "arm,pl330", "arm,primecell"; 621 reg = <0x12680000 0x1000>; 622 interrupts = <0 35 0>; 623 clocks = <&clock CLK_PDMA0>; 624 clock-names = "apb_pclk"; 625 #dma-cells = <1>; 626 #dma-channels = <8>; 627 #dma-requests = <32>; 628 }; 629 630 pdma1: pdma@12690000 { 631 compatible = "arm,pl330", "arm,primecell"; 632 reg = <0x12690000 0x1000>; 633 interrupts = <0 36 0>; 634 clocks = <&clock CLK_PDMA1>; 635 clock-names = "apb_pclk"; 636 #dma-cells = <1>; 637 #dma-channels = <8>; 638 #dma-requests = <32>; 639 }; 640 641 mdma1: mdma@12850000 { 642 compatible = "arm,pl330", "arm,primecell"; 643 reg = <0x12850000 0x1000>; 644 interrupts = <0 34 0>; 645 clocks = <&clock CLK_MDMA>; 646 clock-names = "apb_pclk"; 647 #dma-cells = <1>; 648 #dma-channels = <8>; 649 #dma-requests = <1>; 650 }; 651 }; 652 653 fimd: fimd@11c00000 { 654 compatible = "samsung,exynos4210-fimd"; 655 interrupt-parent = <&combiner>; 656 reg = <0x11c00000 0x20000>; 657 interrupt-names = "fifo", "vsync", "lcd_sys"; 658 interrupts = <11 0>, <11 1>, <11 2>; 659 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; 660 clock-names = "sclk_fimd", "fimd"; 661 power-domains = <&pd_lcd0>;
| 652 compatible = "samsung,exynos4210-pwm"; 653 reg = <0x139D0000 0x1000>; 654 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>; 655 clocks = <&clock CLK_PWM>; 656 clock-names = "timers"; 657 #pwm-cells = <3>; 658 status = "disabled"; 659 }; 660 661 amba { 662 #address-cells = <1>; 663 #size-cells = <1>; 664 compatible = "arm,amba-bus"; 665 interrupt-parent = <&gic>; 666 ranges; 667 668 pdma0: pdma@12680000 { 669 compatible = "arm,pl330", "arm,primecell"; 670 reg = <0x12680000 0x1000>; 671 interrupts = <0 35 0>; 672 clocks = <&clock CLK_PDMA0>; 673 clock-names = "apb_pclk"; 674 #dma-cells = <1>; 675 #dma-channels = <8>; 676 #dma-requests = <32>; 677 }; 678 679 pdma1: pdma@12690000 { 680 compatible = "arm,pl330", "arm,primecell"; 681 reg = <0x12690000 0x1000>; 682 interrupts = <0 36 0>; 683 clocks = <&clock CLK_PDMA1>; 684 clock-names = "apb_pclk"; 685 #dma-cells = <1>; 686 #dma-channels = <8>; 687 #dma-requests = <32>; 688 }; 689 690 mdma1: mdma@12850000 { 691 compatible = "arm,pl330", "arm,primecell"; 692 reg = <0x12850000 0x1000>; 693 interrupts = <0 34 0>; 694 clocks = <&clock CLK_MDMA>; 695 clock-names = "apb_pclk"; 696 #dma-cells = <1>; 697 #dma-channels = <8>; 698 #dma-requests = <1>; 699 }; 700 }; 701 702 fimd: fimd@11c00000 { 703 compatible = "samsung,exynos4210-fimd"; 704 interrupt-parent = <&combiner>; 705 reg = <0x11c00000 0x20000>; 706 interrupt-names = "fifo", "vsync", "lcd_sys"; 707 interrupts = <11 0>, <11 1>, <11 2>; 708 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; 709 clock-names = "sclk_fimd", "fimd"; 710 power-domains = <&pd_lcd0>;
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| 711 iommus = <&sysmmu_fimd0>;
|
662 samsung,sysreg = <&sys_reg>; 663 status = "disabled"; 664 }; 665
| 712 samsung,sysreg = <&sys_reg>; 713 status = "disabled"; 714 }; 715
|
| 716 tmu: tmu@100C0000 { 717 #include "exynos4412-tmu-sensor-conf.dtsi" 718 }; 719 720 jpeg_codec: jpeg-codec@11840000 { 721 compatible = "samsung,exynos4210-jpeg"; 722 reg = <0x11840000 0x1000>; 723 interrupts = <0 88 0>; 724 clocks = <&clock CLK_JPEG>; 725 clock-names = "jpeg"; 726 power-domains = <&pd_cam>; 727 iommus = <&sysmmu_jpeg>; 728 }; 729 730 rotator: rotator@12810000 { 731 compatible = "samsung,exynos4210-rotator"; 732 reg = <0x12810000 0x64>; 733 interrupts = <0 83 0>; 734 clocks = <&clock CLK_ROTATOR>; 735 clock-names = "rotator"; 736 iommus = <&sysmmu_rotator>; 737 }; 738 739 hdmi: hdmi@12D00000 { 740 compatible = "samsung,exynos4210-hdmi"; 741 reg = <0x12D00000 0x70000>; 742 interrupts = <0 92 0>; 743 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy", 744 "mout_hdmi"; 745 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>, 746 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>, 747 <&clock CLK_MOUT_HDMI>; 748 phy = <&hdmi_i2c_phy>; 749 power-domains = <&pd_tv>; 750 samsung,syscon-phandle = <&pmu_system_controller>; 751 status = "disabled"; 752 }; 753 754 mixer: mixer@12C10000 { 755 compatible = "samsung,exynos4210-mixer"; 756 interrupts = <0 91 0>; 757 reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; 758 power-domains = <&pd_tv>; 759 iommus = <&sysmmu_tv>; 760 status = "disabled"; 761 }; 762
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666 ppmu_dmc0: ppmu_dmc0@106a0000 { 667 compatible = "samsung,exynos-ppmu"; 668 reg = <0x106a0000 0x2000>; 669 clocks = <&clock CLK_PPMUDMC0>; 670 clock-names = "ppmu"; 671 status = "disabled"; 672 }; 673 674 ppmu_dmc1: ppmu_dmc1@106b0000 { 675 compatible = "samsung,exynos-ppmu"; 676 reg = <0x106b0000 0x2000>; 677 clocks = <&clock CLK_PPMUDMC1>; 678 clock-names = "ppmu"; 679 status = "disabled"; 680 }; 681 682 ppmu_cpu: ppmu_cpu@106c0000 { 683 compatible = "samsung,exynos-ppmu"; 684 reg = <0x106c0000 0x2000>; 685 clocks = <&clock CLK_PPMUCPU>; 686 clock-names = "ppmu"; 687 status = "disabled"; 688 }; 689 690 ppmu_acp: ppmu_acp@10ae0000 { 691 compatible = "samsung,exynos-ppmu"; 692 reg = <0x106e0000 0x2000>; 693 status = "disabled"; 694 }; 695 696 ppmu_rightbus: ppmu_rightbus@112a0000 { 697 compatible = "samsung,exynos-ppmu"; 698 reg = <0x112a0000 0x2000>; 699 clocks = <&clock CLK_PPMURIGHT>; 700 clock-names = "ppmu"; 701 status = "disabled"; 702 }; 703 704 ppmu_leftbus: ppmu_leftbus0@116a0000 { 705 compatible = "samsung,exynos-ppmu"; 706 reg = <0x116a0000 0x2000>; 707 clocks = <&clock CLK_PPMULEFT>; 708 clock-names = "ppmu"; 709 status = "disabled"; 710 }; 711 712 ppmu_camif: ppmu_camif@11ac0000 { 713 compatible = "samsung,exynos-ppmu"; 714 reg = <0x11ac0000 0x2000>; 715 clocks = <&clock CLK_PPMUCAMIF>; 716 clock-names = "ppmu"; 717 status = "disabled"; 718 }; 719 720 ppmu_lcd0: ppmu_lcd0@11e40000 { 721 compatible = "samsung,exynos-ppmu"; 722 reg = <0x11e40000 0x2000>; 723 clocks = <&clock CLK_PPMULCD0>; 724 clock-names = "ppmu"; 725 status = "disabled"; 726 }; 727 728 ppmu_fsys: ppmu_g3d@12630000 { 729 compatible = "samsung,exynos-ppmu"; 730 reg = <0x12630000 0x2000>; 731 status = "disabled"; 732 }; 733 734 ppmu_image: ppmu_image@12aa0000 { 735 compatible = "samsung,exynos-ppmu"; 736 reg = <0x12aa0000 0x2000>; 737 clocks = <&clock CLK_PPMUIMAGE>; 738 clock-names = "ppmu"; 739 status = "disabled"; 740 }; 741 742 ppmu_tv: ppmu_tv@12e40000 { 743 compatible = "samsung,exynos-ppmu"; 744 reg = <0x12e40000 0x2000>; 745 clocks = <&clock CLK_PPMUTV>; 746 clock-names = "ppmu"; 747 status = "disabled"; 748 }; 749 750 ppmu_g3d: ppmu_g3d@13220000 { 751 compatible = "samsung,exynos-ppmu"; 752 reg = <0x13220000 0x2000>; 753 clocks = <&clock CLK_PPMUG3D>; 754 clock-names = "ppmu"; 755 status = "disabled"; 756 }; 757 758 ppmu_mfc_left: ppmu_mfc_left@13660000 { 759 compatible = "samsung,exynos-ppmu"; 760 reg = <0x13660000 0x2000>; 761 clocks = <&clock CLK_PPMUMFC_L>; 762 clock-names = "ppmu"; 763 status = "disabled"; 764 }; 765 766 ppmu_mfc_right: ppmu_mfc_right@13670000 { 767 compatible = "samsung,exynos-ppmu"; 768 reg = <0x13670000 0x2000>; 769 clocks = <&clock CLK_PPMUMFC_R>; 770 clock-names = "ppmu"; 771 status = "disabled"; 772 };
| 763 ppmu_dmc0: ppmu_dmc0@106a0000 { 764 compatible = "samsung,exynos-ppmu"; 765 reg = <0x106a0000 0x2000>; 766 clocks = <&clock CLK_PPMUDMC0>; 767 clock-names = "ppmu"; 768 status = "disabled"; 769 }; 770 771 ppmu_dmc1: ppmu_dmc1@106b0000 { 772 compatible = "samsung,exynos-ppmu"; 773 reg = <0x106b0000 0x2000>; 774 clocks = <&clock CLK_PPMUDMC1>; 775 clock-names = "ppmu"; 776 status = "disabled"; 777 }; 778 779 ppmu_cpu: ppmu_cpu@106c0000 { 780 compatible = "samsung,exynos-ppmu"; 781 reg = <0x106c0000 0x2000>; 782 clocks = <&clock CLK_PPMUCPU>; 783 clock-names = "ppmu"; 784 status = "disabled"; 785 }; 786 787 ppmu_acp: ppmu_acp@10ae0000 { 788 compatible = "samsung,exynos-ppmu"; 789 reg = <0x106e0000 0x2000>; 790 status = "disabled"; 791 }; 792 793 ppmu_rightbus: ppmu_rightbus@112a0000 { 794 compatible = "samsung,exynos-ppmu"; 795 reg = <0x112a0000 0x2000>; 796 clocks = <&clock CLK_PPMURIGHT>; 797 clock-names = "ppmu"; 798 status = "disabled"; 799 }; 800 801 ppmu_leftbus: ppmu_leftbus0@116a0000 { 802 compatible = "samsung,exynos-ppmu"; 803 reg = <0x116a0000 0x2000>; 804 clocks = <&clock CLK_PPMULEFT>; 805 clock-names = "ppmu"; 806 status = "disabled"; 807 }; 808 809 ppmu_camif: ppmu_camif@11ac0000 { 810 compatible = "samsung,exynos-ppmu"; 811 reg = <0x11ac0000 0x2000>; 812 clocks = <&clock CLK_PPMUCAMIF>; 813 clock-names = "ppmu"; 814 status = "disabled"; 815 }; 816 817 ppmu_lcd0: ppmu_lcd0@11e40000 { 818 compatible = "samsung,exynos-ppmu"; 819 reg = <0x11e40000 0x2000>; 820 clocks = <&clock CLK_PPMULCD0>; 821 clock-names = "ppmu"; 822 status = "disabled"; 823 }; 824 825 ppmu_fsys: ppmu_g3d@12630000 { 826 compatible = "samsung,exynos-ppmu"; 827 reg = <0x12630000 0x2000>; 828 status = "disabled"; 829 }; 830 831 ppmu_image: ppmu_image@12aa0000 { 832 compatible = "samsung,exynos-ppmu"; 833 reg = <0x12aa0000 0x2000>; 834 clocks = <&clock CLK_PPMUIMAGE>; 835 clock-names = "ppmu"; 836 status = "disabled"; 837 }; 838 839 ppmu_tv: ppmu_tv@12e40000 { 840 compatible = "samsung,exynos-ppmu"; 841 reg = <0x12e40000 0x2000>; 842 clocks = <&clock CLK_PPMUTV>; 843 clock-names = "ppmu"; 844 status = "disabled"; 845 }; 846 847 ppmu_g3d: ppmu_g3d@13220000 { 848 compatible = "samsung,exynos-ppmu"; 849 reg = <0x13220000 0x2000>; 850 clocks = <&clock CLK_PPMUG3D>; 851 clock-names = "ppmu"; 852 status = "disabled"; 853 }; 854 855 ppmu_mfc_left: ppmu_mfc_left@13660000 { 856 compatible = "samsung,exynos-ppmu"; 857 reg = <0x13660000 0x2000>; 858 clocks = <&clock CLK_PPMUMFC_L>; 859 clock-names = "ppmu"; 860 status = "disabled"; 861 }; 862 863 ppmu_mfc_right: ppmu_mfc_right@13670000 { 864 compatible = "samsung,exynos-ppmu"; 865 reg = <0x13670000 0x2000>; 866 clocks = <&clock CLK_PPMUMFC_R>; 867 clock-names = "ppmu"; 868 status = "disabled"; 869 };
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| 870 871 sysmmu_mfc_l: sysmmu@13620000 { 872 compatible = "samsung,exynos-sysmmu"; 873 reg = <0x13620000 0x1000>; 874 interrupt-parent = <&combiner>; 875 interrupts = <5 5>; 876 clock-names = "sysmmu", "master"; 877 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>; 878 power-domains = <&pd_mfc>; 879 #iommu-cells = <0>; 880 }; 881 882 sysmmu_mfc_r: sysmmu@13630000 { 883 compatible = "samsung,exynos-sysmmu"; 884 reg = <0x13630000 0x1000>; 885 interrupt-parent = <&combiner>; 886 interrupts = <5 6>; 887 clock-names = "sysmmu", "master"; 888 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>; 889 power-domains = <&pd_mfc>; 890 #iommu-cells = <0>; 891 }; 892 893 sysmmu_tv: sysmmu@12E20000 { 894 compatible = "samsung,exynos-sysmmu"; 895 reg = <0x12E20000 0x1000>; 896 interrupt-parent = <&combiner>; 897 interrupts = <5 4>; 898 clock-names = "sysmmu", "master"; 899 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>; 900 power-domains = <&pd_tv>; 901 #iommu-cells = <0>; 902 }; 903 904 sysmmu_fimc0: sysmmu@11A20000 { 905 compatible = "samsung,exynos-sysmmu"; 906 reg = <0x11A20000 0x1000>; 907 interrupt-parent = <&combiner>; 908 interrupts = <4 2>; 909 clock-names = "sysmmu", "master"; 910 clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>; 911 power-domains = <&pd_cam>; 912 #iommu-cells = <0>; 913 }; 914 915 sysmmu_fimc1: sysmmu@11A30000 { 916 compatible = "samsung,exynos-sysmmu"; 917 reg = <0x11A30000 0x1000>; 918 interrupt-parent = <&combiner>; 919 interrupts = <4 3>; 920 clock-names = "sysmmu", "master"; 921 clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>; 922 power-domains = <&pd_cam>; 923 #iommu-cells = <0>; 924 }; 925 926 sysmmu_fimc2: sysmmu@11A40000 { 927 compatible = "samsung,exynos-sysmmu"; 928 reg = <0x11A40000 0x1000>; 929 interrupt-parent = <&combiner>; 930 interrupts = <4 4>; 931 clock-names = "sysmmu", "master"; 932 clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>; 933 power-domains = <&pd_cam>; 934 #iommu-cells = <0>; 935 }; 936 937 sysmmu_fimc3: sysmmu@11A50000 { 938 compatible = "samsung,exynos-sysmmu"; 939 reg = <0x11A50000 0x1000>; 940 interrupt-parent = <&combiner>; 941 interrupts = <4 5>; 942 clock-names = "sysmmu", "master"; 943 clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>; 944 power-domains = <&pd_cam>; 945 #iommu-cells = <0>; 946 }; 947 948 sysmmu_jpeg: sysmmu@11A60000 { 949 compatible = "samsung,exynos-sysmmu"; 950 reg = <0x11A60000 0x1000>; 951 interrupt-parent = <&combiner>; 952 interrupts = <4 6>; 953 clock-names = "sysmmu", "master"; 954 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>; 955 power-domains = <&pd_cam>; 956 #iommu-cells = <0>; 957 }; 958 959 sysmmu_rotator: sysmmu@12A30000 { 960 compatible = "samsung,exynos-sysmmu"; 961 reg = <0x12A30000 0x1000>; 962 interrupt-parent = <&combiner>; 963 interrupts = <5 0>; 964 clock-names = "sysmmu", "master"; 965 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>; 966 #iommu-cells = <0>; 967 }; 968 969 sysmmu_fimd0: sysmmu@11E20000 { 970 compatible = "samsung,exynos-sysmmu"; 971 reg = <0x11E20000 0x1000>; 972 interrupt-parent = <&combiner>; 973 interrupts = <5 2>; 974 clock-names = "sysmmu", "master"; 975 clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>; 976 power-domains = <&pd_lcd0>; 977 #iommu-cells = <0>; 978 }; 979 980 prng: rng@10830400 { 981 compatible = "samsung,exynos4-rng"; 982 reg = <0x10830400 0x200>; 983 clocks = <&clock CLK_SSS>; 984 clock-names = "secss"; 985 status = "disabled"; 986 };
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773};
| 987};
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