1/*
2 * Samsung's Exynos4 SoC series common device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
--- 24 unchanged lines hidden (view full) ---
33 i2c0 = &i2c_0;
34 i2c1 = &i2c_1;
35 i2c2 = &i2c_2;
36 i2c3 = &i2c_3;
37 i2c4 = &i2c_4;
38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7;
41 csis0 = &csis_0;
42 csis1 = &csis_1;
43 fimc0 = &fimc_0;
44 fimc1 = &fimc_1;
45 fimc2 = &fimc_2;
46 fimc3 = &fimc_3;
47 serial0 = &serial_0;
48 serial1 = &serial_1;
--- 23 unchanged lines hidden (view full) ---
72
73 chipid@10000000 {
74 compatible = "samsung,exynos4210-chipid";
75 reg = <0x10000000 0x100>;
76 };
77
78 mipi_phy: video-phy@10020710 {
79 compatible = "samsung,s5pv210-mipi-video-phy";
80 reg = <0x10020710 8>;
81 #phy-cells = <1>;
82 syscon = <&pmu_system_controller>;
83 };
84
85 pd_mfc: mfc-power-domain@10023C40 {
86 compatible = "samsung,exynos4210-pd";
87 reg = <0x10023C40 0x20>;
88 #power-domain-cells = <0>;
--- 10 unchanged lines hidden (view full) ---
99 reg = <0x10023C80 0x20>;
100 #power-domain-cells = <0>;
101 };
102
103 pd_tv: tv-power-domain@10023C20 {
104 compatible = "samsung,exynos4210-pd";
105 reg = <0x10023C20 0x20>;
106 #power-domain-cells = <0>;
107 };
108
109 pd_cam: cam-power-domain@10023C00 {
110 compatible = "samsung,exynos4210-pd";
111 reg = <0x10023C00 0x20>;
112 #power-domain-cells = <0>;
113 };
114
--- 32 unchanged lines hidden (view full) ---
147 sys_reg: syscon@10010000 {
148 compatible = "samsung,exynos4-sysreg", "syscon";
149 reg = <0x10010000 0x400>;
150 };
151
152 pmu_system_controller: system-controller@10020000 {
153 compatible = "samsung,exynos4210-pmu", "syscon";
154 reg = <0x10020000 0x4000>;
155 };
156
157 dsi_0: dsi@11C80000 {
158 compatible = "samsung,exynos4210-mipi-dsi";
159 reg = <0x11C80000 0x10000>;
160 interrupts = <0 79 0>;
161 power-domains = <&pd_lcd0>;
162 phys = <&mipi_phy 1>;
163 phy-names = "dsim";
164 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
165 clock-names = "bus_clk", "pll_clk";
166 status = "disabled";
167 #address-cells = <1>;
168 #size-cells = <0>;
169 };
170
171 camera {
172 compatible = "samsung,fimc", "simple-bus";
173 status = "disabled";
--- 6 unchanged lines hidden (view full) ---
180 fimc_0: fimc@11800000 {
181 compatible = "samsung,exynos4210-fimc";
182 reg = <0x11800000 0x1000>;
183 interrupts = <0 84 0>;
184 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
185 clock-names = "fimc", "sclk_fimc";
186 power-domains = <&pd_cam>;
187 samsung,sysreg = <&sys_reg>;
188 status = "disabled";
189 };
190
191 fimc_1: fimc@11810000 {
192 compatible = "samsung,exynos4210-fimc";
193 reg = <0x11810000 0x1000>;
194 interrupts = <0 85 0>;
195 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
196 clock-names = "fimc", "sclk_fimc";
197 power-domains = <&pd_cam>;
198 samsung,sysreg = <&sys_reg>;
199 status = "disabled";
200 };
201
202 fimc_2: fimc@11820000 {
203 compatible = "samsung,exynos4210-fimc";
204 reg = <0x11820000 0x1000>;
205 interrupts = <0 86 0>;
206 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
207 clock-names = "fimc", "sclk_fimc";
208 power-domains = <&pd_cam>;
209 samsung,sysreg = <&sys_reg>;
210 status = "disabled";
211 };
212
213 fimc_3: fimc@11830000 {
214 compatible = "samsung,exynos4210-fimc";
215 reg = <0x11830000 0x1000>;
216 interrupts = <0 87 0>;
217 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
218 clock-names = "fimc", "sclk_fimc";
219 power-domains = <&pd_cam>;
220 samsung,sysreg = <&sys_reg>;
221 status = "disabled";
222 };
223
224 csis_0: csis@11880000 {
225 compatible = "samsung,exynos4210-csis";
226 reg = <0x11880000 0x4000>;
227 interrupts = <0 78 0>;
228 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
--- 18 unchanged lines hidden (view full) ---
247 phys = <&mipi_phy 2>;
248 phy-names = "csis";
249 status = "disabled";
250 #address-cells = <1>;
251 #size-cells = <0>;
252 };
253 };
254
255 watchdog@10060000 {
256 compatible = "samsung,s3c2410-wdt";
257 reg = <0x10060000 0x100>;
258 interrupts = <0 43 0>;
259 clocks = <&clock CLK_WDT>;
260 clock-names = "watchdog";
261 status = "disabled";
262 };
263
264 rtc@10070000 {
265 compatible = "samsung,s3c6410-rtc";
266 reg = <0x10070000 0x100>;
267 interrupts = <0 44 0>, <0 45 0>;
268 clocks = <&clock CLK_RTC>;
269 clock-names = "rtc";
270 status = "disabled";
271 };
272
273 keypad@100A0000 {
274 compatible = "samsung,s5pv210-keypad";
275 reg = <0x100A0000 0x100>;
276 interrupts = <0 109 0>;
277 clocks = <&clock CLK_KEYIF>;
278 clock-names = "keypad";
279 status = "disabled";
280 };
281
282 sdhci@12510000 {
283 compatible = "samsung,exynos4210-sdhci";
284 reg = <0x12510000 0x100>;
285 interrupts = <0 73 0>;
286 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
287 clock-names = "hsmmc", "mmc_busclk.2";
288 status = "disabled";
289 };
290
291 sdhci@12520000 {
292 compatible = "samsung,exynos4210-sdhci";
293 reg = <0x12520000 0x100>;
294 interrupts = <0 74 0>;
295 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
296 clock-names = "hsmmc", "mmc_busclk.2";
297 status = "disabled";
298 };
299
300 sdhci@12530000 {
301 compatible = "samsung,exynos4210-sdhci";
302 reg = <0x12530000 0x100>;
303 interrupts = <0 75 0>;
304 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
305 clock-names = "hsmmc", "mmc_busclk.2";
306 status = "disabled";
307 };
308
309 sdhci@12540000 {
310 compatible = "samsung,exynos4210-sdhci";
311 reg = <0x12540000 0x100>;
312 interrupts = <0 76 0>;
313 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
314 clock-names = "hsmmc", "mmc_busclk.2";
315 status = "disabled";
316 };
317
318 exynos_usbphy: exynos-usbphy@125B0000 {
319 compatible = "samsung,exynos4210-usb2-phy";
320 reg = <0x125B0000 0x100>;
321 samsung,pmureg-phandle = <&pmu_system_controller>;
322 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
323 clock-names = "phy", "ref";
324 #phy-cells = <1>;
325 status = "disabled";
326 };
327
328 hsotg@12480000 {
329 compatible = "samsung,s3c6400-hsotg";
330 reg = <0x12480000 0x20000>;
331 interrupts = <0 71 0>;
332 clocks = <&clock CLK_USB_DEVICE>;
333 clock-names = "otg";
334 phys = <&exynos_usbphy 0>;
335 phy-names = "usb2-phy";
336 status = "disabled";
337 };
338
339 ehci@12580000 {
340 compatible = "samsung,exynos4210-ehci";
341 reg = <0x12580000 0x100>;
342 interrupts = <0 70 0>;
343 clocks = <&clock CLK_USB_HOST>;
344 clock-names = "usbhost";
345 status = "disabled";
346 #address-cells = <1>;
347 #size-cells = <0>;
--- 9 unchanged lines hidden (view full) ---
357 };
358 port@2 {
359 reg = <2>;
360 phys = <&exynos_usbphy 3>;
361 status = "disabled";
362 };
363 };
364
365 ohci@12590000 {
366 compatible = "samsung,exynos4210-ohci";
367 reg = <0x12590000 0x100>;
368 interrupts = <0 70 0>;
369 clocks = <&clock CLK_USB_HOST>;
370 clock-names = "usbhost";
371 status = "disabled";
372 #address-cells = <1>;
373 #size-cells = <0>;
--- 32 unchanged lines hidden (view full) ---
406
407 mfc: codec@13400000 {
408 compatible = "samsung,mfc-v5";
409 reg = <0x13400000 0x10000>;
410 interrupts = <0 94 0>;
411 power-domains = <&pd_mfc>;
412 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
413 clock-names = "mfc", "sclk_mfc";
414 status = "disabled";
415 };
416
417 serial_0: serial@13800000 {
418 compatible = "samsung,exynos4210-uart";
419 reg = <0x13800000 0x100>;
420 interrupts = <0 52 0>;
421 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
422 clock-names = "uart", "clk_uart_baud0";
423 status = "disabled";
424 };
425
426 serial_1: serial@13810000 {
427 compatible = "samsung,exynos4210-uart";
428 reg = <0x13810000 0x100>;
429 interrupts = <0 53 0>;
430 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
431 clock-names = "uart", "clk_uart_baud0";
432 status = "disabled";
433 };
434
435 serial_2: serial@13820000 {
436 compatible = "samsung,exynos4210-uart";
437 reg = <0x13820000 0x100>;
438 interrupts = <0 54 0>;
439 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
440 clock-names = "uart", "clk_uart_baud0";
441 status = "disabled";
442 };
443
444 serial_3: serial@13830000 {
445 compatible = "samsung,exynos4210-uart";
446 reg = <0x13830000 0x100>;
447 interrupts = <0 55 0>;
448 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
449 clock-names = "uart", "clk_uart_baud0";
450 status = "disabled";
451 };
452
453 i2c_0: i2c@13860000 {
454 #address-cells = <1>;
455 #size-cells = <0>;
456 compatible = "samsung,s3c2440-i2c";
457 reg = <0x13860000 0x100>;
--- 91 unchanged lines hidden (view full) ---
549 interrupts = <0 65 0>;
550 clocks = <&clock CLK_I2C7>;
551 clock-names = "i2c";
552 pinctrl-names = "default";
553 pinctrl-0 = <&i2c7_bus>;
554 status = "disabled";
555 };
556
557 spi_0: spi@13920000 {
558 compatible = "samsung,exynos4210-spi";
559 reg = <0x13920000 0x100>;
560 interrupts = <0 66 0>;
561 dmas = <&pdma0 7>, <&pdma0 6>;
562 dma-names = "tx", "rx";
563 #address-cells = <1>;
564 #size-cells = <0>;
--- 29 unchanged lines hidden (view full) ---
594 #size-cells = <0>;
595 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
596 clock-names = "spi", "spi_busclk0";
597 pinctrl-names = "default";
598 pinctrl-0 = <&spi2_bus>;
599 status = "disabled";
600 };
601
602 pwm@139D0000 {
603 compatible = "samsung,exynos4210-pwm";
604 reg = <0x139D0000 0x1000>;
605 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
606 clocks = <&clock CLK_PWM>;
607 clock-names = "timers";
608 #pwm-cells = <3>;
609 status = "disabled";
610 };
--- 43 unchanged lines hidden (view full) ---
654 compatible = "samsung,exynos4210-fimd";
655 interrupt-parent = <&combiner>;
656 reg = <0x11c00000 0x20000>;
657 interrupt-names = "fifo", "vsync", "lcd_sys";
658 interrupts = <11 0>, <11 1>, <11 2>;
659 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
660 clock-names = "sclk_fimd", "fimd";
661 power-domains = <&pd_lcd0>;
662 samsung,sysreg = <&sys_reg>;
663 status = "disabled";
664 };
665
666 ppmu_dmc0: ppmu_dmc0@106a0000 {
667 compatible = "samsung,exynos-ppmu";
668 reg = <0x106a0000 0x2000>;
669 clocks = <&clock CLK_PPMUDMC0>;
670 clock-names = "ppmu";
671 status = "disabled";
672 };
673
--- 91 unchanged lines hidden (view full) ---
765
766 ppmu_mfc_right: ppmu_mfc_right@13670000 {
767 compatible = "samsung,exynos-ppmu";
768 reg = <0x13670000 0x2000>;
769 clocks = <&clock CLK_PPMUMFC_R>;
770 clock-names = "ppmu";
771 status = "disabled";
772 };
773};
2 * Samsung's Exynos4 SoC series common device tree source
3 *
4 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2010-2011 Linaro Ltd.
7 * www.linaro.org
8 *
--- 24 unchanged lines hidden (view full) ---
33 i2c0 = &i2c_0;
34 i2c1 = &i2c_1;
35 i2c2 = &i2c_2;
36 i2c3 = &i2c_3;
37 i2c4 = &i2c_4;
38 i2c5 = &i2c_5;
39 i2c6 = &i2c_6;
40 i2c7 = &i2c_7;
41 csis0 = &csis_0;
42 csis1 = &csis_1;
43 fimc0 = &fimc_0;
44 fimc1 = &fimc_1;
45 fimc2 = &fimc_2;
46 fimc3 = &fimc_3;
47 serial0 = &serial_0;
48 serial1 = &serial_1;
--- 23 unchanged lines hidden (view full) ---
72
73 chipid@10000000 {
74 compatible = "samsung,exynos4210-chipid";
75 reg = <0x10000000 0x100>;
76 };
77
78 mipi_phy: video-phy@10020710 {
79 compatible = "samsung,s5pv210-mipi-video-phy";
80 reg = <0x10020710 8>;
81 #phy-cells = <1>;
82 syscon = <&pmu_system_controller>;
83 };
84
85 pd_mfc: mfc-power-domain@10023C40 {
86 compatible = "samsung,exynos4210-pd";
87 reg = <0x10023C40 0x20>;
88 #power-domain-cells = <0>;
--- 10 unchanged lines hidden (view full) ---
99 reg = <0x10023C80 0x20>;
100 #power-domain-cells = <0>;
101 };
102
103 pd_tv: tv-power-domain@10023C20 {
104 compatible = "samsung,exynos4210-pd";
105 reg = <0x10023C20 0x20>;
106 #power-domain-cells = <0>;
107 };
108
109 pd_cam: cam-power-domain@10023C00 {
110 compatible = "samsung,exynos4210-pd";
111 reg = <0x10023C00 0x20>;
112 #power-domain-cells = <0>;
113 };
114
--- 32 unchanged lines hidden (view full) ---
147 sys_reg: syscon@10010000 {
148 compatible = "samsung,exynos4-sysreg", "syscon";
149 reg = <0x10010000 0x400>;
150 };
151
152 pmu_system_controller: system-controller@10020000 {
153 compatible = "samsung,exynos4210-pmu", "syscon";
154 reg = <0x10020000 0x4000>;
155 };
156
157 dsi_0: dsi@11C80000 {
158 compatible = "samsung,exynos4210-mipi-dsi";
159 reg = <0x11C80000 0x10000>;
160 interrupts = <0 79 0>;
161 power-domains = <&pd_lcd0>;
162 phys = <&mipi_phy 1>;
163 phy-names = "dsim";
164 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
165 clock-names = "bus_clk", "pll_clk";
166 status = "disabled";
167 #address-cells = <1>;
168 #size-cells = <0>;
169 };
170
171 camera {
172 compatible = "samsung,fimc", "simple-bus";
173 status = "disabled";
--- 6 unchanged lines hidden (view full) ---
180 fimc_0: fimc@11800000 {
181 compatible = "samsung,exynos4210-fimc";
182 reg = <0x11800000 0x1000>;
183 interrupts = <0 84 0>;
184 clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
185 clock-names = "fimc", "sclk_fimc";
186 power-domains = <&pd_cam>;
187 samsung,sysreg = <&sys_reg>;
188 status = "disabled";
189 };
190
191 fimc_1: fimc@11810000 {
192 compatible = "samsung,exynos4210-fimc";
193 reg = <0x11810000 0x1000>;
194 interrupts = <0 85 0>;
195 clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
196 clock-names = "fimc", "sclk_fimc";
197 power-domains = <&pd_cam>;
198 samsung,sysreg = <&sys_reg>;
199 status = "disabled";
200 };
201
202 fimc_2: fimc@11820000 {
203 compatible = "samsung,exynos4210-fimc";
204 reg = <0x11820000 0x1000>;
205 interrupts = <0 86 0>;
206 clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
207 clock-names = "fimc", "sclk_fimc";
208 power-domains = <&pd_cam>;
209 samsung,sysreg = <&sys_reg>;
210 status = "disabled";
211 };
212
213 fimc_3: fimc@11830000 {
214 compatible = "samsung,exynos4210-fimc";
215 reg = <0x11830000 0x1000>;
216 interrupts = <0 87 0>;
217 clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
218 clock-names = "fimc", "sclk_fimc";
219 power-domains = <&pd_cam>;
220 samsung,sysreg = <&sys_reg>;
221 status = "disabled";
222 };
223
224 csis_0: csis@11880000 {
225 compatible = "samsung,exynos4210-csis";
226 reg = <0x11880000 0x4000>;
227 interrupts = <0 78 0>;
228 clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
--- 18 unchanged lines hidden (view full) ---
247 phys = <&mipi_phy 2>;
248 phy-names = "csis";
249 status = "disabled";
250 #address-cells = <1>;
251 #size-cells = <0>;
252 };
253 };
254
255 watchdog@10060000 {
256 compatible = "samsung,s3c2410-wdt";
257 reg = <0x10060000 0x100>;
258 interrupts = <0 43 0>;
259 clocks = <&clock CLK_WDT>;
260 clock-names = "watchdog";
261 status = "disabled";
262 };
263
264 rtc@10070000 {
265 compatible = "samsung,s3c6410-rtc";
266 reg = <0x10070000 0x100>;
267 interrupts = <0 44 0>, <0 45 0>;
268 clocks = <&clock CLK_RTC>;
269 clock-names = "rtc";
270 status = "disabled";
271 };
272
273 keypad@100A0000 {
274 compatible = "samsung,s5pv210-keypad";
275 reg = <0x100A0000 0x100>;
276 interrupts = <0 109 0>;
277 clocks = <&clock CLK_KEYIF>;
278 clock-names = "keypad";
279 status = "disabled";
280 };
281
282 sdhci@12510000 {
283 compatible = "samsung,exynos4210-sdhci";
284 reg = <0x12510000 0x100>;
285 interrupts = <0 73 0>;
286 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
287 clock-names = "hsmmc", "mmc_busclk.2";
288 status = "disabled";
289 };
290
291 sdhci@12520000 {
292 compatible = "samsung,exynos4210-sdhci";
293 reg = <0x12520000 0x100>;
294 interrupts = <0 74 0>;
295 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
296 clock-names = "hsmmc", "mmc_busclk.2";
297 status = "disabled";
298 };
299
300 sdhci@12530000 {
301 compatible = "samsung,exynos4210-sdhci";
302 reg = <0x12530000 0x100>;
303 interrupts = <0 75 0>;
304 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
305 clock-names = "hsmmc", "mmc_busclk.2";
306 status = "disabled";
307 };
308
309 sdhci@12540000 {
310 compatible = "samsung,exynos4210-sdhci";
311 reg = <0x12540000 0x100>;
312 interrupts = <0 76 0>;
313 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
314 clock-names = "hsmmc", "mmc_busclk.2";
315 status = "disabled";
316 };
317
318 exynos_usbphy: exynos-usbphy@125B0000 {
319 compatible = "samsung,exynos4210-usb2-phy";
320 reg = <0x125B0000 0x100>;
321 samsung,pmureg-phandle = <&pmu_system_controller>;
322 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
323 clock-names = "phy", "ref";
324 #phy-cells = <1>;
325 status = "disabled";
326 };
327
328 hsotg@12480000 {
329 compatible = "samsung,s3c6400-hsotg";
330 reg = <0x12480000 0x20000>;
331 interrupts = <0 71 0>;
332 clocks = <&clock CLK_USB_DEVICE>;
333 clock-names = "otg";
334 phys = <&exynos_usbphy 0>;
335 phy-names = "usb2-phy";
336 status = "disabled";
337 };
338
339 ehci@12580000 {
340 compatible = "samsung,exynos4210-ehci";
341 reg = <0x12580000 0x100>;
342 interrupts = <0 70 0>;
343 clocks = <&clock CLK_USB_HOST>;
344 clock-names = "usbhost";
345 status = "disabled";
346 #address-cells = <1>;
347 #size-cells = <0>;
--- 9 unchanged lines hidden (view full) ---
357 };
358 port@2 {
359 reg = <2>;
360 phys = <&exynos_usbphy 3>;
361 status = "disabled";
362 };
363 };
364
365 ohci@12590000 {
366 compatible = "samsung,exynos4210-ohci";
367 reg = <0x12590000 0x100>;
368 interrupts = <0 70 0>;
369 clocks = <&clock CLK_USB_HOST>;
370 clock-names = "usbhost";
371 status = "disabled";
372 #address-cells = <1>;
373 #size-cells = <0>;
--- 32 unchanged lines hidden (view full) ---
406
407 mfc: codec@13400000 {
408 compatible = "samsung,mfc-v5";
409 reg = <0x13400000 0x10000>;
410 interrupts = <0 94 0>;
411 power-domains = <&pd_mfc>;
412 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
413 clock-names = "mfc", "sclk_mfc";
414 status = "disabled";
415 };
416
417 serial_0: serial@13800000 {
418 compatible = "samsung,exynos4210-uart";
419 reg = <0x13800000 0x100>;
420 interrupts = <0 52 0>;
421 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
422 clock-names = "uart", "clk_uart_baud0";
423 status = "disabled";
424 };
425
426 serial_1: serial@13810000 {
427 compatible = "samsung,exynos4210-uart";
428 reg = <0x13810000 0x100>;
429 interrupts = <0 53 0>;
430 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
431 clock-names = "uart", "clk_uart_baud0";
432 status = "disabled";
433 };
434
435 serial_2: serial@13820000 {
436 compatible = "samsung,exynos4210-uart";
437 reg = <0x13820000 0x100>;
438 interrupts = <0 54 0>;
439 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
440 clock-names = "uart", "clk_uart_baud0";
441 status = "disabled";
442 };
443
444 serial_3: serial@13830000 {
445 compatible = "samsung,exynos4210-uart";
446 reg = <0x13830000 0x100>;
447 interrupts = <0 55 0>;
448 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
449 clock-names = "uart", "clk_uart_baud0";
450 status = "disabled";
451 };
452
453 i2c_0: i2c@13860000 {
454 #address-cells = <1>;
455 #size-cells = <0>;
456 compatible = "samsung,s3c2440-i2c";
457 reg = <0x13860000 0x100>;
--- 91 unchanged lines hidden (view full) ---
549 interrupts = <0 65 0>;
550 clocks = <&clock CLK_I2C7>;
551 clock-names = "i2c";
552 pinctrl-names = "default";
553 pinctrl-0 = <&i2c7_bus>;
554 status = "disabled";
555 };
556
557 spi_0: spi@13920000 {
558 compatible = "samsung,exynos4210-spi";
559 reg = <0x13920000 0x100>;
560 interrupts = <0 66 0>;
561 dmas = <&pdma0 7>, <&pdma0 6>;
562 dma-names = "tx", "rx";
563 #address-cells = <1>;
564 #size-cells = <0>;
--- 29 unchanged lines hidden (view full) ---
594 #size-cells = <0>;
595 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
596 clock-names = "spi", "spi_busclk0";
597 pinctrl-names = "default";
598 pinctrl-0 = <&spi2_bus>;
599 status = "disabled";
600 };
601
602 pwm@139D0000 {
603 compatible = "samsung,exynos4210-pwm";
604 reg = <0x139D0000 0x1000>;
605 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
606 clocks = <&clock CLK_PWM>;
607 clock-names = "timers";
608 #pwm-cells = <3>;
609 status = "disabled";
610 };
--- 43 unchanged lines hidden (view full) ---
654 compatible = "samsung,exynos4210-fimd";
655 interrupt-parent = <&combiner>;
656 reg = <0x11c00000 0x20000>;
657 interrupt-names = "fifo", "vsync", "lcd_sys";
658 interrupts = <11 0>, <11 1>, <11 2>;
659 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
660 clock-names = "sclk_fimd", "fimd";
661 power-domains = <&pd_lcd0>;
662 samsung,sysreg = <&sys_reg>;
663 status = "disabled";
664 };
665
666 ppmu_dmc0: ppmu_dmc0@106a0000 {
667 compatible = "samsung,exynos-ppmu";
668 reg = <0x106a0000 0x2000>;
669 clocks = <&clock CLK_PPMUDMC0>;
670 clock-names = "ppmu";
671 status = "disabled";
672 };
673
--- 91 unchanged lines hidden (view full) ---
765
766 ppmu_mfc_right: ppmu_mfc_right@13670000 {
767 compatible = "samsung,exynos-ppmu";
768 reg = <0x13670000 0x2000>;
769 clocks = <&clock CLK_PPMUMFC_R>;
770 clock-names = "ppmu";
771 status = "disabled";
772 };
773};