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exynos3250.dtsi (279385) exynos3250.dtsi (295436)
1/*
2 * Samsung's Exynos3250 SoC device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic

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13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include "skeleton.dtsi"
1/*
2 * Samsung's Exynos3250 SoC device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic

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13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include "skeleton.dtsi"
21#include "exynos4-cpu-thermal.dtsi"
21#include <dt-bindings/clock/exynos3250.h>
22
23/ {
24 compatible = "samsung,exynos3250";
25 interrupt-parent = <&gic>;
26
27 aliases {
28 pinctrl0 = &pinctrl_0;

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47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 cpu0: cpu@0 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a7";
53 reg = <0>;
54 clock-frequency = <1000000000>;
22#include <dt-bindings/clock/exynos3250.h>
23
24/ {
25 compatible = "samsung,exynos3250";
26 interrupt-parent = <&gic>;
27
28 aliases {
29 pinctrl0 = &pinctrl_0;

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48 #address-cells = <1>;
49 #size-cells = <0>;
50
51 cpu0: cpu@0 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a7";
54 reg = <0>;
55 clock-frequency = <1000000000>;
56 clocks = <&cmu CLK_ARM_CLK>;
57 clock-names = "cpu";
58 #cooling-cells = <2>;
59
60 operating-points = <
61 1000000 1150000
62 900000 1112500
63 800000 1075000
64 700000 1037500
65 600000 1000000
66 500000 962500
67 400000 925000
68 300000 887500
69 200000 850000
70 100000 850000
71 >;
55 };
56
57 cpu1: cpu@1 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a7";
60 reg = <1>;
61 clock-frequency = <1000000000>;
62 };

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125 sys_reg: syscon@10010000 {
126 compatible = "samsung,exynos3-sysreg", "syscon";
127 reg = <0x10010000 0x400>;
128 };
129
130 pmu_system_controller: system-controller@10020000 {
131 compatible = "samsung,exynos3250-pmu", "syscon";
132 reg = <0x10020000 0x4000>;
72 };
73
74 cpu1: cpu@1 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a7";
77 reg = <1>;
78 clock-frequency = <1000000000>;
79 };

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142 sys_reg: syscon@10010000 {
143 compatible = "samsung,exynos3-sysreg", "syscon";
144 reg = <0x10010000 0x400>;
145 };
146
147 pmu_system_controller: system-controller@10020000 {
148 compatible = "samsung,exynos3250-pmu", "syscon";
149 reg = <0x10020000 0x4000>;
150 interrupt-controller;
151 #interrupt-cells = <3>;
152 interrupt-parent = <&gic>;
133 };
134
153 };
154
155 poweroff: syscon-poweroff {
156 compatible = "syscon-poweroff";
157 regmap = <&pmu_system_controller>;
158 offset = <0x330C>; /* PS_HOLD_CONTROL */
159 mask = <0x5200>; /* Reset value */
160 };
161
162 reboot: syscon-reboot {
163 compatible = "syscon-reboot";
164 regmap = <&pmu_system_controller>;
165 offset = <0x0400>; /* SWRESET */
166 mask = <0x1>;
167 };
168
135 mipi_phy: video-phy@10020710 {
136 compatible = "samsung,s5pv210-mipi-video-phy";
169 mipi_phy: video-phy@10020710 {
170 compatible = "samsung,s5pv210-mipi-video-phy";
137 reg = <0x10020710 8>;
138 #phy-cells = <1>;
171 #phy-cells = <1>;
172 syscon = <&pmu_system_controller>;
139 };
140
141 pd_cam: cam-power-domain@10023C00 {
142 compatible = "samsung,exynos4210-pd";
143 reg = <0x10023C00 0x20>;
144 #power-domain-cells = <0>;
145 };
146

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167 reg = <0x10023CA0 0x20>;
168 #power-domain-cells = <0>;
169 };
170
171 cmu: clock-controller@10030000 {
172 compatible = "samsung,exynos3250-cmu";
173 reg = <0x10030000 0x20000>;
174 #clock-cells = <1>;
173 };
174
175 pd_cam: cam-power-domain@10023C00 {
176 compatible = "samsung,exynos4210-pd";
177 reg = <0x10023C00 0x20>;
178 #power-domain-cells = <0>;
179 };
180

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201 reg = <0x10023CA0 0x20>;
202 #power-domain-cells = <0>;
203 };
204
205 cmu: clock-controller@10030000 {
206 compatible = "samsung,exynos3250-cmu";
207 reg = <0x10030000 0x20000>;
208 #clock-cells = <1>;
209 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
210 <&cmu CLK_MOUT_ACLK_266_SUB>;
211 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
212 <&cmu CLK_FIN_PLL>;
175 };
176
177 cmu_dmc: clock-controller@105C0000 {
178 compatible = "samsung,exynos3250-cmu-dmc";
179 reg = <0x105C0000 0x2000>;
180 #clock-cells = <1>;
181 };
182
183 rtc: rtc@10070000 {
213 };
214
215 cmu_dmc: clock-controller@105C0000 {
216 compatible = "samsung,exynos3250-cmu-dmc";
217 reg = <0x105C0000 0x2000>;
218 #clock-cells = <1>;
219 };
220
221 rtc: rtc@10070000 {
184 compatible = "samsung,exynos3250-rtc";
222 compatible = "samsung,s3c6410-rtc";
185 reg = <0x10070000 0x100>;
186 interrupts = <0 73 0>, <0 74 0>;
223 reg = <0x10070000 0x100>;
224 interrupts = <0 73 0>, <0 74 0>;
225 interrupt-parent = <&pmu_system_controller>;
187 status = "disabled";
188 };
189
190 tmu: tmu@100C0000 {
191 compatible = "samsung,exynos3250-tmu";
192 reg = <0x100C0000 0x100>;
193 interrupts = <0 216 0>;
194 clocks = <&cmu CLK_TMU_APBIF>;
195 clock-names = "tmu_apbif";
226 status = "disabled";
227 };
228
229 tmu: tmu@100C0000 {
230 compatible = "samsung,exynos3250-tmu";
231 reg = <0x100C0000 0x100>;
232 interrupts = <0 216 0>;
233 clocks = <&cmu CLK_TMU_APBIF>;
234 clock-names = "tmu_apbif";
235 #include "exynos4412-tmu-sensor-conf.dtsi"
196 status = "disabled";
197 };
198
199 gic: interrupt-controller@10481000 {
200 compatible = "arm,cortex-a15-gic";
201 #interrupt-cells = <3>;
202 interrupt-controller;
203 reg = <0x10481000 0x1000>,

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228 };
229
230 pinctrl_0: pinctrl@11400000 {
231 compatible = "samsung,exynos3250-pinctrl";
232 reg = <0x11400000 0x1000>;
233 interrupts = <0 240 0>;
234 };
235
236 status = "disabled";
237 };
238
239 gic: interrupt-controller@10481000 {
240 compatible = "arm,cortex-a15-gic";
241 #interrupt-cells = <3>;
242 interrupt-controller;
243 reg = <0x10481000 0x1000>,

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268 };
269
270 pinctrl_0: pinctrl@11400000 {
271 compatible = "samsung,exynos3250-pinctrl";
272 reg = <0x11400000 0x1000>;
273 interrupts = <0 240 0>;
274 };
275
276 jpeg: codec@11830000 {
277 compatible = "samsung,exynos3250-jpeg";
278 reg = <0x11830000 0x1000>;
279 interrupts = <0 171 0>;
280 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
281 clock-names = "jpeg", "sclk";
282 power-domains = <&pd_cam>;
283 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
284 assigned-clock-rates = <0>, <150000000>;
285 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
286 iommus = <&sysmmu_jpeg>;
287 status = "disabled";
288 };
289
290 sysmmu_jpeg: sysmmu@11A60000 {
291 compatible = "samsung,exynos-sysmmu";
292 reg = <0x11a60000 0x1000>;
293 interrupts = <0 156 0>, <0 161 0>;
294 clock-names = "sysmmu", "master";
295 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
296 power-domains = <&pd_cam>;
297 #iommu-cells = <0>;
298 };
299
236 fimd: fimd@11c00000 {
237 compatible = "samsung,exynos3250-fimd";
238 reg = <0x11c00000 0x30000>;
239 interrupt-names = "fifo", "vsync", "lcd_sys";
240 interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
241 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
242 clock-names = "sclk_fimd", "fimd";
243 power-domains = <&pd_lcd0>;
300 fimd: fimd@11c00000 {
301 compatible = "samsung,exynos3250-fimd";
302 reg = <0x11c00000 0x30000>;
303 interrupt-names = "fifo", "vsync", "lcd_sys";
304 interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
305 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
306 clock-names = "sclk_fimd", "fimd";
307 power-domains = <&pd_lcd0>;
308 iommus = <&sysmmu_fimd0>;
244 samsung,sysreg = <&sys_reg>;
245 status = "disabled";
246 };
247
248 dsi_0: dsi@11C80000 {
249 compatible = "samsung,exynos3250-mipi-dsi";
250 reg = <0x11C80000 0x10000>;
251 interrupts = <0 83 0>;
252 samsung,phy-type = <0>;
253 power-domains = <&pd_lcd0>;
254 phys = <&mipi_phy 1>;
255 phy-names = "dsim";
256 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
257 clock-names = "bus_clk", "pll_clk";
258 #address-cells = <1>;
259 #size-cells = <0>;
260 status = "disabled";
261 };
262
309 samsung,sysreg = <&sys_reg>;
310 status = "disabled";
311 };
312
313 dsi_0: dsi@11C80000 {
314 compatible = "samsung,exynos3250-mipi-dsi";
315 reg = <0x11C80000 0x10000>;
316 interrupts = <0 83 0>;
317 samsung,phy-type = <0>;
318 power-domains = <&pd_lcd0>;
319 phys = <&mipi_phy 1>;
320 phy-names = "dsim";
321 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
322 clock-names = "bus_clk", "pll_clk";
323 #address-cells = <1>;
324 #size-cells = <0>;
325 status = "disabled";
326 };
327
328 sysmmu_fimd0: sysmmu@11E20000 {
329 compatible = "samsung,exynos-sysmmu";
330 reg = <0x11e20000 0x1000>;
331 interrupts = <0 80 0>, <0 81 0>;
332 clock-names = "sysmmu", "master";
333 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
334 power-domains = <&pd_lcd0>;
335 #iommu-cells = <0>;
336 };
337
263 hsotg: hsotg@12480000 {
264 compatible = "snps,dwc2";
265 reg = <0x12480000 0x20000>;
266 interrupts = <0 141 0>;
267 clocks = <&cmu CLK_USBOTG>;
268 clock-names = "otg";
269 phys = <&exynos_usbphy 0>;
270 phy-names = "usb2-phy";
271 status = "disabled";
272 };
273
274 mshc_0: mshc@12510000 {
338 hsotg: hsotg@12480000 {
339 compatible = "snps,dwc2";
340 reg = <0x12480000 0x20000>;
341 interrupts = <0 141 0>;
342 clocks = <&cmu CLK_USBOTG>;
343 clock-names = "otg";
344 phys = <&exynos_usbphy 0>;
345 phy-names = "usb2-phy";
346 status = "disabled";
347 };
348
349 mshc_0: mshc@12510000 {
275 compatible = "samsung,exynos5250-dw-mshc";
350 compatible = "samsung,exynos5420-dw-mshc";
276 reg = <0x12510000 0x1000>;
277 interrupts = <0 142 0>;
278 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
279 clock-names = "biu", "ciu";
280 fifo-depth = <0x80>;
281 #address-cells = <1>;
282 #size-cells = <0>;
283 status = "disabled";
284 };
285
286 mshc_1: mshc@12520000 {
351 reg = <0x12510000 0x1000>;
352 interrupts = <0 142 0>;
353 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
354 clock-names = "biu", "ciu";
355 fifo-depth = <0x80>;
356 #address-cells = <1>;
357 #size-cells = <0>;
358 status = "disabled";
359 };
360
361 mshc_1: mshc@12520000 {
287 compatible = "samsung,exynos5250-dw-mshc";
362 compatible = "samsung,exynos5420-dw-mshc";
288 reg = <0x12520000 0x1000>;
289 interrupts = <0 143 0>;
290 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
291 clock-names = "biu", "ciu";
292 fifo-depth = <0x80>;
293 #address-cells = <1>;
294 #size-cells = <0>;
295 status = "disabled";

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349
350 mfc: codec@13400000 {
351 compatible = "samsung,mfc-v7";
352 reg = <0x13400000 0x10000>;
353 interrupts = <0 102 0>;
354 clock-names = "mfc", "sclk_mfc";
355 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
356 power-domains = <&pd_mfc>;
363 reg = <0x12520000 0x1000>;
364 interrupts = <0 143 0>;
365 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
366 clock-names = "biu", "ciu";
367 fifo-depth = <0x80>;
368 #address-cells = <1>;
369 #size-cells = <0>;
370 status = "disabled";

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424
425 mfc: codec@13400000 {
426 compatible = "samsung,mfc-v7";
427 reg = <0x13400000 0x10000>;
428 interrupts = <0 102 0>;
429 clock-names = "mfc", "sclk_mfc";
430 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
431 power-domains = <&pd_mfc>;
432 iommus = <&sysmmu_mfc>;
357 status = "disabled";
358 };
359
433 status = "disabled";
434 };
435
436 sysmmu_mfc: sysmmu@13620000 {
437 compatible = "samsung,exynos-sysmmu";
438 reg = <0x13620000 0x1000>;
439 interrupts = <0 96 0>, <0 98 0>;
440 clock-names = "sysmmu", "master";
441 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
442 power-domains = <&pd_mfc>;
443 #iommu-cells = <0>;
444 };
445
360 serial_0: serial@13800000 {
361 compatible = "samsung,exynos4210-uart";
362 reg = <0x13800000 0x100>;
363 interrupts = <0 109 0>;
364 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
365 clock-names = "uart", "clk_uart_baud0";
366 pinctrl-names = "default";
367 pinctrl-0 = <&uart0_data &uart0_fctl>;

--- 254 unchanged lines hidden --- 		446 serial_0: serial@13800000 {
447 compatible = "samsung,exynos4210-uart";
448 reg = <0x13800000 0x100>;
449 interrupts = <0 109 0>;
450 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
451 clock-names = "uart", "clk_uart_baud0";
452 pinctrl-names = "default";
453 pinctrl-0 = <&uart0_data &uart0_fctl>;

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