1/*
2 * Samsung's Exynos3250 SoC device tree source
3 *
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
8 * based board files can include this file and provide values for board specfic

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13 * nodes can be added to this file.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include "skeleton.dtsi"
21#include <dt-bindings/clock/exynos3250.h>
22
23/ {
24 compatible = "samsung,exynos3250";
25 interrupt-parent = <&gic>;
26
27 aliases {
28 pinctrl0 = &pinctrl_0;

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47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 cpu0: cpu@0 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a7";
53 reg = <0>;
54 clock-frequency = <1000000000>;
55 };
56
57 cpu1: cpu@1 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a7";
60 reg = <1>;
61 clock-frequency = <1000000000>;
62 };

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125 sys_reg: syscon@10010000 {
126 compatible = "samsung,exynos3-sysreg", "syscon";
127 reg = <0x10010000 0x400>;
128 };
129
130 pmu_system_controller: system-controller@10020000 {
131 compatible = "samsung,exynos3250-pmu", "syscon";
132 reg = <0x10020000 0x4000>;
133 };
134
135 mipi_phy: video-phy@10020710 {
136 compatible = "samsung,s5pv210-mipi-video-phy";
137 reg = <0x10020710 8>;
138 #phy-cells = <1>;
139 };
140
141 pd_cam: cam-power-domain@10023C00 {
142 compatible = "samsung,exynos4210-pd";
143 reg = <0x10023C00 0x20>;
144 #power-domain-cells = <0>;
145 };
146

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167 reg = <0x10023CA0 0x20>;
168 #power-domain-cells = <0>;
169 };
170
171 cmu: clock-controller@10030000 {
172 compatible = "samsung,exynos3250-cmu";
173 reg = <0x10030000 0x20000>;
174 #clock-cells = <1>;
175 };
176
177 cmu_dmc: clock-controller@105C0000 {
178 compatible = "samsung,exynos3250-cmu-dmc";
179 reg = <0x105C0000 0x2000>;
180 #clock-cells = <1>;
181 };
182
183 rtc: rtc@10070000 {
184 compatible = "samsung,exynos3250-rtc";
185 reg = <0x10070000 0x100>;
186 interrupts = <0 73 0>, <0 74 0>;
187 status = "disabled";
188 };
189
190 tmu: tmu@100C0000 {
191 compatible = "samsung,exynos3250-tmu";
192 reg = <0x100C0000 0x100>;
193 interrupts = <0 216 0>;
194 clocks = <&cmu CLK_TMU_APBIF>;
195 clock-names = "tmu_apbif";
196 status = "disabled";
197 };
198
199 gic: interrupt-controller@10481000 {
200 compatible = "arm,cortex-a15-gic";
201 #interrupt-cells = <3>;
202 interrupt-controller;
203 reg = <0x10481000 0x1000>,

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228 };
229
230 pinctrl_0: pinctrl@11400000 {
231 compatible = "samsung,exynos3250-pinctrl";
232 reg = <0x11400000 0x1000>;
233 interrupts = <0 240 0>;
234 };
235
236 fimd: fimd@11c00000 {
237 compatible = "samsung,exynos3250-fimd";
238 reg = <0x11c00000 0x30000>;
239 interrupt-names = "fifo", "vsync", "lcd_sys";
240 interrupts = <0 84 0>, <0 85 0>, <0 86 0>;
241 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
242 clock-names = "sclk_fimd", "fimd";
243 power-domains = <&pd_lcd0>;
244 samsung,sysreg = <&sys_reg>;
245 status = "disabled";
246 };
247
248 dsi_0: dsi@11C80000 {
249 compatible = "samsung,exynos3250-mipi-dsi";
250 reg = <0x11C80000 0x10000>;
251 interrupts = <0 83 0>;
252 samsung,phy-type = <0>;
253 power-domains = <&pd_lcd0>;
254 phys = <&mipi_phy 1>;
255 phy-names = "dsim";
256 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
257 clock-names = "bus_clk", "pll_clk";
258 #address-cells = <1>;
259 #size-cells = <0>;
260 status = "disabled";
261 };
262
263 hsotg: hsotg@12480000 {
264 compatible = "snps,dwc2";
265 reg = <0x12480000 0x20000>;
266 interrupts = <0 141 0>;
267 clocks = <&cmu CLK_USBOTG>;
268 clock-names = "otg";
269 phys = <&exynos_usbphy 0>;
270 phy-names = "usb2-phy";
271 status = "disabled";
272 };
273
274 mshc_0: mshc@12510000 {
275 compatible = "samsung,exynos5250-dw-mshc";
276 reg = <0x12510000 0x1000>;
277 interrupts = <0 142 0>;
278 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
279 clock-names = "biu", "ciu";
280 fifo-depth = <0x80>;
281 #address-cells = <1>;
282 #size-cells = <0>;
283 status = "disabled";
284 };
285
286 mshc_1: mshc@12520000 {
287 compatible = "samsung,exynos5250-dw-mshc";
288 reg = <0x12520000 0x1000>;
289 interrupts = <0 143 0>;
290 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
291 clock-names = "biu", "ciu";
292 fifo-depth = <0x80>;
293 #address-cells = <1>;
294 #size-cells = <0>;
295 status = "disabled";

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349
350 mfc: codec@13400000 {
351 compatible = "samsung,mfc-v7";
352 reg = <0x13400000 0x10000>;
353 interrupts = <0 102 0>;
354 clock-names = "mfc", "sclk_mfc";
355 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
356 power-domains = <&pd_mfc>;
357 status = "disabled";
358 };
359
360 serial_0: serial@13800000 {
361 compatible = "samsung,exynos4210-uart";
362 reg = <0x13800000 0x100>;
363 interrupts = <0 109 0>;
364 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
365 clock-names = "uart", "clk_uart_baud0";
366 pinctrl-names = "default";
367 pinctrl-0 = <&uart0_data &uart0_fctl>;

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