1/*
2 * Device Tree Source for the EMEV2 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.

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16 interrupt-parent = <&gic>;
17
18 aliases {
19 gpio0 = &gpio0;
20 gpio1 = &gpio1;
21 gpio2 = &gpio2;
22 gpio3 = &gpio3;
23 gpio4 = &gpio4;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 cpu@0 {
31 device_type = "cpu";

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37 device_type = "cpu";
38 compatible = "arm,cortex-a9";
39 reg = <1>;
40 clock-frequency = <533000000>;
41 };
42 };
43
44 gic: interrupt-controller@e0020000 {
45 compatible = "arm,cortex-a9-gic";
46 interrupt-controller;
47 #interrupt-cells = <3>;
48 reg = <0xe0028000 0x1000>,
49 <0xe0020000 0x0100>;
50 };
51
52 pmu {
53 compatible = "arm,cortex-a9-pmu";

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61 #address-cells = <2>;
62 #size-cells = <0>;
63
64 c32ki: c32ki {
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
67 #clock-cells = <0>;
68 };
69 pll3_fo: pll3_fo {
70 compatible = "fixed-factor-clock";
71 clocks = <&c32ki>;
72 clock-div = <1>;
73 clock-mult = <7000>;
74 #clock-cells = <0>;
75 };
76 usia_u0_sclkdiv: usia_u0_sclkdiv {

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164 uart3: serial@e1050000 {
165 compatible = "renesas,em-uart";
166 reg = <0xe1050000 0x38>;
167 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&usib_u3_sclk>;
169 clock-names = "sclk";
170 };
171
172 gpio0: gpio@e0050000 {
173 compatible = "renesas,em-gio";
174 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
175 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>,
176 <0 68 IRQ_TYPE_LEVEL_HIGH>;
177 gpio-controller;
178 #gpio-cells = <2>;
179 ngpios = <32>;
180 interrupt-controller;
181 #interrupt-cells = <2>;
182 };
183 gpio1: gpio@e0050080 {
184 compatible = "renesas,em-gio";
185 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
186 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>,
187 <0 70 IRQ_TYPE_LEVEL_HIGH>;
188 gpio-controller;
189 #gpio-cells = <2>;
190 ngpios = <32>;
191 interrupt-controller;
192 #interrupt-cells = <2>;
193 };
194 gpio2: gpio@e0050100 {
195 compatible = "renesas,em-gio";
196 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
197 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,
198 <0 72 IRQ_TYPE_LEVEL_HIGH>;
199 gpio-controller;
200 #gpio-cells = <2>;
201 ngpios = <32>;
202 interrupt-controller;
203 #interrupt-cells = <2>;
204 };
205 gpio3: gpio@e0050180 {
206 compatible = "renesas,em-gio";
207 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
208 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>,
209 <0 74 IRQ_TYPE_LEVEL_HIGH>;
210 gpio-controller;
211 #gpio-cells = <2>;
212 ngpios = <32>;
213 interrupt-controller;
214 #interrupt-cells = <2>;
215 };
216 gpio4: gpio@e0050200 {
217 compatible = "renesas,em-gio";
218 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
219 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>,
220 <0 76 IRQ_TYPE_LEVEL_HIGH>;
221 gpio-controller;
222 #gpio-cells = <2>;
223 ngpios = <31>;
224 interrupt-controller;
225 #interrupt-cells = <2>;
226 };
227};