1/*
2 * Device Tree Source for the EMEV2 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.

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16 interrupt-parent = <&gic>;
17
18 aliases {
19 gpio0 = &gpio0;
20 gpio1 = &gpio1;
21 gpio2 = &gpio2;
22 gpio3 = &gpio3;
23 gpio4 = &gpio4;
24 i2c0 = &iic0;
25 i2c1 = &iic1;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 cpu@0 {
33 device_type = "cpu";

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39 device_type = "cpu";
40 compatible = "arm,cortex-a9";
41 reg = <1>;
42 clock-frequency = <533000000>;
43 };
44 };
45
46 gic: interrupt-controller@e0020000 {
47 compatible = "arm,pl390";
48 interrupt-controller;
49 #interrupt-cells = <3>;
50 reg = <0xe0028000 0x1000>,
51 <0xe0020000 0x0100>;
52 };
53
54 pmu {
55 compatible = "arm,cortex-a9-pmu";

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63 #address-cells = <2>;
64 #size-cells = <0>;
65
66 c32ki: c32ki {
67 compatible = "fixed-clock";
68 clock-frequency = <32768>;
69 #clock-cells = <0>;
70 };
71 iic0_sclkdiv: iic0_sclkdiv {
72 compatible = "renesas,emev2-smu-clkdiv";
73 reg = <0x624 0>;
74 clocks = <&pll3_fo>;
75 #clock-cells = <0>;
76 };
77 iic0_sclk: iic0_sclk {
78 compatible = "renesas,emev2-smu-gclk";
79 reg = <0x48c 1>;
80 clocks = <&iic0_sclkdiv>;
81 #clock-cells = <0>;
82 };
83 iic1_sclkdiv: iic1_sclkdiv {
84 compatible = "renesas,emev2-smu-clkdiv";
85 reg = <0x624 16>;
86 clocks = <&pll3_fo>;
87 #clock-cells = <0>;
88 };
89 iic1_sclk: iic1_sclk {
90 compatible = "renesas,emev2-smu-gclk";
91 reg = <0x490 1>;
92 clocks = <&iic1_sclkdiv>;
93 #clock-cells = <0>;
94 };
95 pll3_fo: pll3_fo {
96 compatible = "fixed-factor-clock";
97 clocks = <&c32ki>;
98 clock-div = <1>;
99 clock-mult = <7000>;
100 #clock-cells = <0>;
101 };
102 usia_u0_sclkdiv: usia_u0_sclkdiv {

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190 uart3: serial@e1050000 {
191 compatible = "renesas,em-uart";
192 reg = <0xe1050000 0x38>;
193 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&usib_u3_sclk>;
195 clock-names = "sclk";
196 };
197
198 pfc: pfc@e0140200 {
199 compatible = "renesas,pfc-emev2";
200 reg = <0xe0140200 0x100>;
201 };
202
203 gpio0: gpio@e0050000 {
204 compatible = "renesas,em-gio";
205 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
206 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>,
207 <0 68 IRQ_TYPE_LEVEL_HIGH>;
208 gpio-controller;
209 gpio-ranges = <&pfc 0 0 32>;
210 #gpio-cells = <2>;
211 ngpios = <32>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
214 };
215 gpio1: gpio@e0050080 {
216 compatible = "renesas,em-gio";
217 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
218 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>,
219 <0 70 IRQ_TYPE_LEVEL_HIGH>;
220 gpio-controller;
221 gpio-ranges = <&pfc 0 32 32>;
222 #gpio-cells = <2>;
223 ngpios = <32>;
224 interrupt-controller;
225 #interrupt-cells = <2>;
226 };
227 gpio2: gpio@e0050100 {
228 compatible = "renesas,em-gio";
229 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
230 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,
231 <0 72 IRQ_TYPE_LEVEL_HIGH>;
232 gpio-controller;
233 gpio-ranges = <&pfc 0 64 32>;
234 #gpio-cells = <2>;
235 ngpios = <32>;
236 interrupt-controller;
237 #interrupt-cells = <2>;
238 };
239 gpio3: gpio@e0050180 {
240 compatible = "renesas,em-gio";
241 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
242 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>,
243 <0 74 IRQ_TYPE_LEVEL_HIGH>;
244 gpio-controller;
245 gpio-ranges = <&pfc 0 96 32>;
246 #gpio-cells = <2>;
247 ngpios = <32>;
248 interrupt-controller;
249 #interrupt-cells = <2>;
250 };
251 gpio4: gpio@e0050200 {
252 compatible = "renesas,em-gio";
253 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
254 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>,
255 <0 76 IRQ_TYPE_LEVEL_HIGH>;
256 gpio-controller;
257 gpio-ranges = <&pfc 0 128 31>;
258 #gpio-cells = <2>;
259 ngpios = <31>;
260 interrupt-controller;
261 #interrupt-cells = <2>;
262 };
263
264 iic0: i2c@e0070000 {
265 #address-cells = <1>;
266 #size-cells = <0>;
267 compatible = "renesas,iic-emev2";
268 reg = <0xe0070000 0x28>;
269 interrupts = <0 32 IRQ_TYPE_EDGE_RISING>;
270 clocks = <&iic0_sclk>;
271 clock-names = "sclk";
272 status = "disabled";
273 };
274
275 iic1: i2c@e10a0000 {
276 #address-cells = <1>;
277 #size-cells = <0>;
278 compatible = "renesas,iic-emev2";
279 reg = <0xe10a0000 0x28>;
280 interrupts = <0 33 IRQ_TYPE_EDGE_RISING>;
281 clocks = <&iic1_sclk>;
282 clock-names = "sclk";
283 status = "disabled";
284 };
285};