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1/*
2 * Device Tree Source for DRA7xx clock data
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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238 clocks = <&dpll_abe_x2_ck>;
239 ti,max-div = <31>;
240 ti,autoidle-shift = <8>;
241 reg = <0x01f4>;
242 ti,index-starts-at-one;
243 ti,invert-autoidle-bit;
244 };
245
246 dpll_core_byp_mux: dpll_core_byp_mux {
247 #clock-cells = <0>;
248 compatible = "ti,mux-clock";
249 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
250 ti,bit-shift = <23>;
251 reg = <0x012c>;
252 };
253
254 dpll_core_ck: dpll_core_ck {
255 #clock-cells = <0>;
256 compatible = "ti,omap4-dpll-core-clock";
249 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
257 clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
258 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
259 };
260
261 dpll_core_x2_ck: dpll_core_x2_ck {
262 #clock-cells = <0>;
263 compatible = "ti,omap4-dpll-x2-clock";
264 clocks = <&dpll_core_ck>;
265 };

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312 dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
313 #clock-cells = <0>;
314 compatible = "fixed-factor-clock";
315 clocks = <&dpll_core_h12x2_ck>;
316 clock-mult = <1>;
317 clock-div = <1>;
318 };
319
320 dpll_dsp_byp_mux: dpll_dsp_byp_mux {
321 #clock-cells = <0>;
322 compatible = "ti,mux-clock";
323 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
324 ti,bit-shift = <23>;
325 reg = <0x0240>;
326 };
327
328 dpll_dsp_ck: dpll_dsp_ck {
329 #clock-cells = <0>;
330 compatible = "ti,omap4-dpll-clock";
315 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
331 clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
332 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
333 };
334
335 dpll_dsp_m2_ck: dpll_dsp_m2_ck {
336 #clock-cells = <0>;
337 compatible = "ti,divider-clock";
338 clocks = <&dpll_dsp_ck>;
339 ti,max-div = <31>;

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346 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
347 #clock-cells = <0>;
348 compatible = "fixed-factor-clock";
349 clocks = <&dpll_core_h12x2_ck>;
350 clock-mult = <1>;
351 clock-div = <1>;
352 };
353
354 dpll_iva_byp_mux: dpll_iva_byp_mux {
355 #clock-cells = <0>;
356 compatible = "ti,mux-clock";
357 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
358 ti,bit-shift = <23>;
359 reg = <0x01ac>;
360 };
361
362 dpll_iva_ck: dpll_iva_ck {
363 #clock-cells = <0>;
364 compatible = "ti,omap4-dpll-clock";
341 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
365 clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
366 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
367 };
368
369 dpll_iva_m2_ck: dpll_iva_m2_ck {
370 #clock-cells = <0>;
371 compatible = "ti,divider-clock";
372 clocks = <&dpll_iva_ck>;
373 ti,max-div = <31>;

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380 iva_dclk: iva_dclk {
381 #clock-cells = <0>;
382 compatible = "fixed-factor-clock";
383 clocks = <&dpll_iva_m2_ck>;
384 clock-mult = <1>;
385 clock-div = <1>;
386 };
387
388 dpll_gpu_byp_mux: dpll_gpu_byp_mux {
389 #clock-cells = <0>;
390 compatible = "ti,mux-clock";
391 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
392 ti,bit-shift = <23>;
393 reg = <0x02e4>;
394 };
395
396 dpll_gpu_ck: dpll_gpu_ck {
397 #clock-cells = <0>;
398 compatible = "ti,omap4-dpll-clock";
367 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
399 clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
400 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
401 };
402
403 dpll_gpu_m2_ck: dpll_gpu_m2_ck {
404 #clock-cells = <0>;
405 compatible = "ti,divider-clock";
406 clocks = <&dpll_gpu_ck>;
407 ti,max-div = <31>;

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425 core_dpll_out_dclk_div: core_dpll_out_dclk_div {
426 #clock-cells = <0>;
427 compatible = "fixed-factor-clock";
428 clocks = <&dpll_core_m2_ck>;
429 clock-mult = <1>;
430 clock-div = <1>;
431 };
432
433 dpll_ddr_byp_mux: dpll_ddr_byp_mux {
434 #clock-cells = <0>;
435 compatible = "ti,mux-clock";
436 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
437 ti,bit-shift = <23>;
438 reg = <0x021c>;
439 };
440
441 dpll_ddr_ck: dpll_ddr_ck {
442 #clock-cells = <0>;
443 compatible = "ti,omap4-dpll-clock";
404 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
444 clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
445 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
446 };
447
448 dpll_ddr_m2_ck: dpll_ddr_m2_ck {
449 #clock-cells = <0>;
450 compatible = "ti,divider-clock";
451 clocks = <&dpll_ddr_ck>;
452 ti,max-div = <31>;
453 ti,autoidle-shift = <8>;
454 reg = <0x0220>;
455 ti,index-starts-at-one;
456 ti,invert-autoidle-bit;
457 };
458
459 dpll_gmac_byp_mux: dpll_gmac_byp_mux {
460 #clock-cells = <0>;
461 compatible = "ti,mux-clock";
462 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
463 ti,bit-shift = <23>;
464 reg = <0x02b4>;
465 };
466
467 dpll_gmac_ck: dpll_gmac_ck {
468 #clock-cells = <0>;
469 compatible = "ti,omap4-dpll-clock";
422 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
470 clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
471 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
472 };
473
474 dpll_gmac_m2_ck: dpll_gmac_m2_ck {
475 #clock-cells = <0>;
476 compatible = "ti,divider-clock";
477 clocks = <&dpll_gmac_ck>;
478 ti,max-div = <31>;

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525 eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
526 #clock-cells = <0>;
527 compatible = "fixed-factor-clock";
528 clocks = <&dpll_core_h12x2_ck>;
529 clock-mult = <1>;
530 clock-div = <1>;
531 };
532
533 dpll_eve_byp_mux: dpll_eve_byp_mux {
534 #clock-cells = <0>;
535 compatible = "ti,mux-clock";
536 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
537 ti,bit-shift = <23>;
538 reg = <0x0290>;
539 };
540
541 dpll_eve_ck: dpll_eve_ck {
542 #clock-cells = <0>;
543 compatible = "ti,omap4-dpll-clock";
488 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
544 clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
545 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
546 };
547
548 dpll_eve_m2_ck: dpll_eve_m2_ck {
549 #clock-cells = <0>;
550 compatible = "ti,divider-clock";
551 clocks = <&dpll_eve_ck>;
552 ti,max-div = <31>;

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1300 apll_pcie_m2_ck: apll_pcie_m2_ck {
1301 #clock-cells = <0>;
1302 compatible = "fixed-factor-clock";
1303 clocks = <&apll_pcie_ck>;
1304 clock-mult = <1>;
1305 clock-div = <1>;
1306 };
1307
1308 dpll_per_byp_mux: dpll_per_byp_mux {
1309 #clock-cells = <0>;
1310 compatible = "ti,mux-clock";
1311 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1312 ti,bit-shift = <23>;
1313 reg = <0x014c>;
1314 };
1315
1316 dpll_per_ck: dpll_per_ck {
1317 #clock-cells = <0>;
1318 compatible = "ti,omap4-dpll-clock";
1255 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1319 clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1320 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1321 };
1322
1323 dpll_per_m2_ck: dpll_per_m2_ck {
1324 #clock-cells = <0>;
1325 compatible = "ti,divider-clock";
1326 clocks = <&dpll_per_ck>;
1327 ti,max-div = <31>;

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1334 func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1335 #clock-cells = <0>;
1336 compatible = "fixed-factor-clock";
1337 clocks = <&dpll_per_m2_ck>;
1338 clock-mult = <1>;
1339 clock-div = <1>;
1340 };
1341
1342 dpll_usb_byp_mux: dpll_usb_byp_mux {
1343 #clock-cells = <0>;
1344 compatible = "ti,mux-clock";
1345 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1346 ti,bit-shift = <23>;
1347 reg = <0x018c>;
1348 };
1349
1350 dpll_usb_ck: dpll_usb_ck {
1351 #clock-cells = <0>;
1352 compatible = "ti,omap4-dpll-j-type-clock";
1281 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1353 clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1354 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1355 };
1356
1357 dpll_usb_m2_ck: dpll_usb_m2_ck {
1358 #clock-cells = <0>;
1359 compatible = "ti,divider-clock";
1360 clocks = <&dpll_usb_ck>;
1361 ti,max-div = <127>;

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1488 l3init_60m_fclk: l3init_60m_fclk {
1489 #clock-cells = <0>;
1490 compatible = "ti,divider-clock";
1491 clocks = <&dpll_usb_m2_ck>;
1492 reg = <0x0104>;
1493 ti,dividers = <1>, <8>;
1494 };
1495
1496 clkout2_clk: clkout2_clk {
1497 #clock-cells = <0>;
1498 compatible = "ti,gate-clock";
1499 clocks = <&clkoutmux2_clk_mux>;
1500 ti,bit-shift = <8>;
1501 reg = <0x06b0>;
1502 };
1503
1504 l3init_960m_gfclk: l3init_960m_gfclk {
1505 #clock-cells = <0>;
1506 compatible = "ti,gate-clock";
1507 clocks = <&dpll_usb_clkdcoldo>;
1508 ti,bit-shift = <8>;
1509 reg = <0x06c0>;
1510 };
1511

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1526 };
1527
1528 dss_dss_clk: dss_dss_clk {
1529 #clock-cells = <0>;
1530 compatible = "ti,gate-clock";
1531 clocks = <&dpll_per_h12x2_ck>;
1532 ti,bit-shift = <8>;
1533 reg = <0x1120>;
1534 ti,set-rate-parent;
1535 };
1536
1537 dss_hdmi_clk: dss_hdmi_clk {
1538 #clock-cells = <0>;
1539 compatible = "ti,gate-clock";
1540 clocks = <&hdmi_dpll_clk_mux>;
1541 ti,bit-shift = <10>;
1542 reg = <0x1120>;

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2132};
2133
2134&cm_core_clockdomains {
2135 coreaon_clkdm: coreaon_clkdm {
2136 compatible = "ti,clockdomain";
2137 clocks = <&dpll_usb_ck>;
2138 };
2139};
2140
2141&scm_conf_clocks {
2142 dss_deshdcp_clk: dss_deshdcp_clk {
2143 #clock-cells = <0>;
2144 compatible = "ti,gate-clock";
2145 clocks = <&l3_iclk_div>;
2146 ti,bit-shift = <0>;
2147 reg = <0x558>;
2148 };
2149};