245a246,253
> dpll_core_byp_mux: dpll_core_byp_mux {
> #clock-cells = <0>;
> compatible = "ti,mux-clock";
> clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
> ti,bit-shift = <23>;
> reg = <0x012c>;
> };
>
249c257
< clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
---
> clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
311a320,327
> dpll_dsp_byp_mux: dpll_dsp_byp_mux {
> #clock-cells = <0>;
> compatible = "ti,mux-clock";
> clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
> ti,bit-shift = <23>;
> reg = <0x0240>;
> };
>
315c331
< clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
---
> clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
337a354,361
> dpll_iva_byp_mux: dpll_iva_byp_mux {
> #clock-cells = <0>;
> compatible = "ti,mux-clock";
> clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
> ti,bit-shift = <23>;
> reg = <0x01ac>;
> };
>
341c365
< clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
---
> clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
363a388,395
> dpll_gpu_byp_mux: dpll_gpu_byp_mux {
> #clock-cells = <0>;
> compatible = "ti,mux-clock";
> clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
> ti,bit-shift = <23>;
> reg = <0x02e4>;
> };
>
367c399
< clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
---
> clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
400a433,440
> dpll_ddr_byp_mux: dpll_ddr_byp_mux {
> #clock-cells = <0>;
> compatible = "ti,mux-clock";
> clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
> ti,bit-shift = <23>;
> reg = <0x021c>;
> };
>
404c444
< clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
---
> clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
418a459,466
> dpll_gmac_byp_mux: dpll_gmac_byp_mux {
> #clock-cells = <0>;
> compatible = "ti,mux-clock";
> clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
> ti,bit-shift = <23>;
> reg = <0x02b4>;
> };
>
422c470
< clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
---
> clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
484a533,540
> dpll_eve_byp_mux: dpll_eve_byp_mux {
> #clock-cells = <0>;
> compatible = "ti,mux-clock";
> clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
> ti,bit-shift = <23>;
> reg = <0x0290>;
> };
>
488c544
< clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
---
> clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
1251a1308,1315
> dpll_per_byp_mux: dpll_per_byp_mux {
> #clock-cells = <0>;
> compatible = "ti,mux-clock";
> clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
> ti,bit-shift = <23>;
> reg = <0x014c>;
> };
>
1255c1319
< clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
---
> clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1277a1342,1349
> dpll_usb_byp_mux: dpll_usb_byp_mux {
> #clock-cells = <0>;
> compatible = "ti,mux-clock";
> clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
> ti,bit-shift = <23>;
> reg = <0x018c>;
> };
>
1281c1353
< clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
---
> clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1423a1496,1503
> clkout2_clk: clkout2_clk {
> #clock-cells = <0>;
> compatible = "ti,gate-clock";
> clocks = <&clkoutmux2_clk_mux>;
> ti,bit-shift = <8>;
> reg = <0x06b0>;
> };
>
1453a1534
> ti,set-rate-parent;
2058a2140,2149
>
> &scm_conf_clocks {
> dss_deshdcp_clk: dss_deshdcp_clk {
> #clock-cells = <0>;
> compatible = "ti,gate-clock";
> clocks = <&l3_iclk_div>;
> ti,bit-shift = <0>;
> reg = <0x558>;
> };
> };