1/*
2 * Device Tree Source for DRA7xx clock data
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.

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238 clocks = <&dpll_abe_x2_ck>;
239 ti,max-div = <31>;
240 ti,autoidle-shift = <8>;
241 reg = <0x01f4>;
242 ti,index-starts-at-one;
243 ti,invert-autoidle-bit;
244 };
245
246 dpll_core_ck: dpll_core_ck {
247 #clock-cells = <0>;
248 compatible = "ti,omap4-dpll-core-clock";
249 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
250 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
251 };
252
253 dpll_core_x2_ck: dpll_core_x2_ck {
254 #clock-cells = <0>;
255 compatible = "ti,omap4-dpll-x2-clock";
256 clocks = <&dpll_core_ck>;
257 };

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304 dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
305 #clock-cells = <0>;
306 compatible = "fixed-factor-clock";
307 clocks = <&dpll_core_h12x2_ck>;
308 clock-mult = <1>;
309 clock-div = <1>;
310 };
311
312 dpll_dsp_ck: dpll_dsp_ck {
313 #clock-cells = <0>;
314 compatible = "ti,omap4-dpll-clock";
315 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
316 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
317 };
318
319 dpll_dsp_m2_ck: dpll_dsp_m2_ck {
320 #clock-cells = <0>;
321 compatible = "ti,divider-clock";
322 clocks = <&dpll_dsp_ck>;
323 ti,max-div = <31>;

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330 iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
331 #clock-cells = <0>;
332 compatible = "fixed-factor-clock";
333 clocks = <&dpll_core_h12x2_ck>;
334 clock-mult = <1>;
335 clock-div = <1>;
336 };
337
338 dpll_iva_ck: dpll_iva_ck {
339 #clock-cells = <0>;
340 compatible = "ti,omap4-dpll-clock";
341 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
342 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
343 };
344
345 dpll_iva_m2_ck: dpll_iva_m2_ck {
346 #clock-cells = <0>;
347 compatible = "ti,divider-clock";
348 clocks = <&dpll_iva_ck>;
349 ti,max-div = <31>;

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356 iva_dclk: iva_dclk {
357 #clock-cells = <0>;
358 compatible = "fixed-factor-clock";
359 clocks = <&dpll_iva_m2_ck>;
360 clock-mult = <1>;
361 clock-div = <1>;
362 };
363
364 dpll_gpu_ck: dpll_gpu_ck {
365 #clock-cells = <0>;
366 compatible = "ti,omap4-dpll-clock";
367 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
368 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
369 };
370
371 dpll_gpu_m2_ck: dpll_gpu_m2_ck {
372 #clock-cells = <0>;
373 compatible = "ti,divider-clock";
374 clocks = <&dpll_gpu_ck>;
375 ti,max-div = <31>;

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393 core_dpll_out_dclk_div: core_dpll_out_dclk_div {
394 #clock-cells = <0>;
395 compatible = "fixed-factor-clock";
396 clocks = <&dpll_core_m2_ck>;
397 clock-mult = <1>;
398 clock-div = <1>;
399 };
400
401 dpll_ddr_ck: dpll_ddr_ck {
402 #clock-cells = <0>;
403 compatible = "ti,omap4-dpll-clock";
404 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
405 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
406 };
407
408 dpll_ddr_m2_ck: dpll_ddr_m2_ck {
409 #clock-cells = <0>;
410 compatible = "ti,divider-clock";
411 clocks = <&dpll_ddr_ck>;
412 ti,max-div = <31>;
413 ti,autoidle-shift = <8>;
414 reg = <0x0220>;
415 ti,index-starts-at-one;
416 ti,invert-autoidle-bit;
417 };
418
419 dpll_gmac_ck: dpll_gmac_ck {
420 #clock-cells = <0>;
421 compatible = "ti,omap4-dpll-clock";
422 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
423 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
424 };
425
426 dpll_gmac_m2_ck: dpll_gmac_m2_ck {
427 #clock-cells = <0>;
428 compatible = "ti,divider-clock";
429 clocks = <&dpll_gmac_ck>;
430 ti,max-div = <31>;

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477 eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
478 #clock-cells = <0>;
479 compatible = "fixed-factor-clock";
480 clocks = <&dpll_core_h12x2_ck>;
481 clock-mult = <1>;
482 clock-div = <1>;
483 };
484
485 dpll_eve_ck: dpll_eve_ck {
486 #clock-cells = <0>;
487 compatible = "ti,omap4-dpll-clock";
488 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
489 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
490 };
491
492 dpll_eve_m2_ck: dpll_eve_m2_ck {
493 #clock-cells = <0>;
494 compatible = "ti,divider-clock";
495 clocks = <&dpll_eve_ck>;
496 ti,max-div = <31>;

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1244 apll_pcie_m2_ck: apll_pcie_m2_ck {
1245 #clock-cells = <0>;
1246 compatible = "fixed-factor-clock";
1247 clocks = <&apll_pcie_ck>;
1248 clock-mult = <1>;
1249 clock-div = <1>;
1250 };
1251
1252 dpll_per_ck: dpll_per_ck {
1253 #clock-cells = <0>;
1254 compatible = "ti,omap4-dpll-clock";
1255 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1256 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1257 };
1258
1259 dpll_per_m2_ck: dpll_per_m2_ck {
1260 #clock-cells = <0>;
1261 compatible = "ti,divider-clock";
1262 clocks = <&dpll_per_ck>;
1263 ti,max-div = <31>;

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1270 func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1271 #clock-cells = <0>;
1272 compatible = "fixed-factor-clock";
1273 clocks = <&dpll_per_m2_ck>;
1274 clock-mult = <1>;
1275 clock-div = <1>;
1276 };
1277
1278 dpll_usb_ck: dpll_usb_ck {
1279 #clock-cells = <0>;
1280 compatible = "ti,omap4-dpll-j-type-clock";
1281 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1282 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1283 };
1284
1285 dpll_usb_m2_ck: dpll_usb_m2_ck {
1286 #clock-cells = <0>;
1287 compatible = "ti,divider-clock";
1288 clocks = <&dpll_usb_ck>;
1289 ti,max-div = <127>;

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1416 l3init_60m_fclk: l3init_60m_fclk {
1417 #clock-cells = <0>;
1418 compatible = "ti,divider-clock";
1419 clocks = <&dpll_usb_m2_ck>;
1420 reg = <0x0104>;
1421 ti,dividers = <1>, <8>;
1422 };
1423
1424 l3init_960m_gfclk: l3init_960m_gfclk {
1425 #clock-cells = <0>;
1426 compatible = "ti,gate-clock";
1427 clocks = <&dpll_usb_clkdcoldo>;
1428 ti,bit-shift = <8>;
1429 reg = <0x06c0>;
1430 };
1431

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1446 };
1447
1448 dss_dss_clk: dss_dss_clk {
1449 #clock-cells = <0>;
1450 compatible = "ti,gate-clock";
1451 clocks = <&dpll_per_h12x2_ck>;
1452 ti,bit-shift = <8>;
1453 reg = <0x1120>;
1454 };
1455
1456 dss_hdmi_clk: dss_hdmi_clk {
1457 #clock-cells = <0>;
1458 compatible = "ti,gate-clock";
1459 clocks = <&hdmi_dpll_clk_mux>;
1460 ti,bit-shift = <10>;
1461 reg = <0x1120>;

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2051};
2052
2053&cm_core_clockdomains {
2054 coreaon_clkdm: coreaon_clkdm {
2055 compatible = "ti,clockdomain";
2056 clocks = <&dpll_usb_ck>;
2057 };
2058};