33a34,38
>
> /* cooling options */
> cooling-min-level = <0>;
> cooling-max-level = <2>;
> #cooling-cells = <2>; /* min followed by max */
44,45c49,51
< interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
< <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
---
> interrupt-parent = <&wakeupgen>;
> interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
48a55,59
> dsp2_system: dsp_system@41500000 {
> compatible = "syscon";
> reg = <0x41500000 0x100>;
> };
>
62c73,78
< interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
---
> interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "peripheral",
> "host",
> "otg";
67a84,103
>
> mmu0_dsp2: mmu@41501000 {
> compatible = "ti,dra7-dsp-iommu";
> reg = <0x41501000 0x100>;
> interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> ti,hwmods = "mmu0_dsp2";
> #iommu-cells = <0>;
> ti,syscon-mmuconfig = <&dsp2_system 0x0>;
> status = "disabled";
> };
>
> mmu1_dsp2: mmu@41502000 {
> compatible = "ti,dra7-dsp-iommu";
> reg = <0x41502000 0x100>;
> interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> ti,hwmods = "mmu1_dsp2";
> #iommu-cells = <0>;
> ti,syscon-mmuconfig = <&dsp2_system 0x1>;
> status = "disabled";
> };
69a106,146
>
> &dss {
> reg = <0x58000000 0x80>,
> <0x58004054 0x4>,
> <0x58004300 0x20>,
> <0x58005054 0x4>,
> <0x58005300 0x20>;
> reg-names = "dss", "pll1_clkctrl", "pll1",
> "pll2_clkctrl", "pll2";
>
> clocks = <&dss_dss_clk>,
> <&dss_video1_clk>,
> <&dss_video2_clk>;
> clock-names = "fck", "video1_clk", "video2_clk";
> };
>
> &mailbox5 {
> mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
> ti,mbox-tx = <6 2 2>;
> ti,mbox-rx = <4 2 2>;
> status = "disabled";
> };
> mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
> ti,mbox-tx = <5 2 2>;
> ti,mbox-rx = <1 2 2>;
> status = "disabled";
> };
> };
>
> &mailbox6 {
> mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
> ti,mbox-tx = <6 2 2>;
> ti,mbox-rx = <4 2 2>;
> status = "disabled";
> };
> mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
> ti,mbox-tx = <5 2 2>;
> ti,mbox-rx = <1 2 2>;
> status = "disabled";
> };
> };
>
> /* cooling options */
> cooling-min-level = <0>;
> cooling-max-level = <2>;
> #cooling-cells = <2>; /* min followed by max */
44,45c49,51
< interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>,
< <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
---
> interrupt-parent = <&wakeupgen>;
> interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
48a55,59
> dsp2_system: dsp_system@41500000 {
> compatible = "syscon";
> reg = <0x41500000 0x100>;
> };
>
62c73,78
< interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
---
> interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "peripheral",
> "host",
> "otg";
67a84,103
>
> mmu0_dsp2: mmu@41501000 {
> compatible = "ti,dra7-dsp-iommu";
> reg = <0x41501000 0x100>;
> interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
> ti,hwmods = "mmu0_dsp2";
> #iommu-cells = <0>;
> ti,syscon-mmuconfig = <&dsp2_system 0x0>;
> status = "disabled";
> };
>
> mmu1_dsp2: mmu@41502000 {
> compatible = "ti,dra7-dsp-iommu";
> reg = <0x41502000 0x100>;
> interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> ti,hwmods = "mmu1_dsp2";
> #iommu-cells = <0>;
> ti,syscon-mmuconfig = <&dsp2_system 0x1>;
> status = "disabled";
> };
69a106,146
>
> &dss {
> reg = <0x58000000 0x80>,
> <0x58004054 0x4>,
> <0x58004300 0x20>,
> <0x58005054 0x4>,
> <0x58005300 0x20>;
> reg-names = "dss", "pll1_clkctrl", "pll1",
> "pll2_clkctrl", "pll2";
>
> clocks = <&dss_dss_clk>,
> <&dss_video1_clk>,
> <&dss_video2_clk>;
> clock-names = "fck", "video1_clk", "video2_clk";
> };
>
> &mailbox5 {
> mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
> ti,mbox-tx = <6 2 2>;
> ti,mbox-rx = <4 2 2>;
> status = "disabled";
> };
> mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
> ti,mbox-tx = <5 2 2>;
> ti,mbox-rx = <1 2 2>;
> status = "disabled";
> };
> };
>
> &mailbox6 {
> mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
> ti,mbox-tx = <6 2 2>;
> ti,mbox-rx = <4 2 2>;
> status = "disabled";
> };
> mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
> ti,mbox-tx = <5 2 2>;
> ti,mbox-rx = <1 2 2>;
> status = "disabled";
> };
> };