1/* 2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * Based on "omap4.dtsi" 8 */ 9 10#include "dra7.dtsi" 11 12/ { 13 compatible = "ti,dra742", "ti,dra74", "ti,dra7"; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a15"; 22 reg = <0>; 23 24 operating-points = < 25 /* kHz uV */ 26 1000000 1060000 27 1176000 1160000 28 >; 29 30 clocks = <&dpll_mpu_ck>; 31 clock-names = "cpu"; 32 33 clock-latency = <300000>; /* From omap-cpufreq driver */
| 1/* 2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * Based on "omap4.dtsi" 8 */ 9 10#include "dra7.dtsi" 11 12/ { 13 compatible = "ti,dra742", "ti,dra74", "ti,dra7"; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a15"; 22 reg = <0>; 23 24 operating-points = < 25 /* kHz uV */ 26 1000000 1060000 27 1176000 1160000 28 >; 29 30 clocks = <&dpll_mpu_ck>; 31 clock-names = "cpu"; 32 33 clock-latency = <300000>; /* From omap-cpufreq driver */
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| 34 35 /* cooling options */ 36 cooling-min-level = <0>; 37 cooling-max-level = <2>; 38 #cooling-cells = <2>; /* min followed by max */
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34 }; 35 cpu@1 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a15"; 38 reg = <1>; 39 }; 40 }; 41 42 pmu { 43 compatible = "arm,cortex-a15-pmu";
| 39 }; 40 cpu@1 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a15"; 43 reg = <1>; 44 }; 45 }; 46 47 pmu { 48 compatible = "arm,cortex-a15-pmu";
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44 interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>;
| 49 interrupt-parent = <&wakeupgen>; 50 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
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46 }; 47 48 ocp {
| 52 }; 53 54 ocp {
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| 55 dsp2_system: dsp_system@41500000 { 56 compatible = "syscon"; 57 reg = <0x41500000 0x100>; 58 }; 59
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49 omap_dwc3_4: omap_dwc3_4@48940000 { 50 compatible = "ti,dwc3"; 51 ti,hwmods = "usb_otg_ss4"; 52 reg = <0x48940000 0x10000>; 53 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 utmi-mode = <2>; 57 ranges; 58 status = "disabled"; 59 usb4: usb@48950000 { 60 compatible = "snps,dwc3"; 61 reg = <0x48950000 0x17000>;
| 60 omap_dwc3_4: omap_dwc3_4@48940000 { 61 compatible = "ti,dwc3"; 62 ti,hwmods = "usb_otg_ss4"; 63 reg = <0x48940000 0x10000>; 64 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 65 #address-cells = <1>; 66 #size-cells = <1>; 67 utmi-mode = <2>; 68 ranges; 69 status = "disabled"; 70 usb4: usb@48950000 { 71 compatible = "snps,dwc3"; 72 reg = <0x48950000 0x17000>;
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62 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
| 73 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 76 interrupt-names = "peripheral", 77 "host", 78 "otg";
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63 tx-fifo-resize; 64 maximum-speed = "high-speed"; 65 dr_mode = "otg"; 66 }; 67 };
| 79 tx-fifo-resize; 80 maximum-speed = "high-speed"; 81 dr_mode = "otg"; 82 }; 83 };
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| 84 85 mmu0_dsp2: mmu@41501000 { 86 compatible = "ti,dra7-dsp-iommu"; 87 reg = <0x41501000 0x100>; 88 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 89 ti,hwmods = "mmu0_dsp2"; 90 #iommu-cells = <0>; 91 ti,syscon-mmuconfig = <&dsp2_system 0x0>; 92 status = "disabled"; 93 }; 94 95 mmu1_dsp2: mmu@41502000 { 96 compatible = "ti,dra7-dsp-iommu"; 97 reg = <0x41502000 0x100>; 98 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 99 ti,hwmods = "mmu1_dsp2"; 100 #iommu-cells = <0>; 101 ti,syscon-mmuconfig = <&dsp2_system 0x1>; 102 status = "disabled"; 103 };
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68 }; 69};
| 104 }; 105};
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| 106 107&dss { 108 reg = <0x58000000 0x80>, 109 <0x58004054 0x4>, 110 <0x58004300 0x20>, 111 <0x58005054 0x4>, 112 <0x58005300 0x20>; 113 reg-names = "dss", "pll1_clkctrl", "pll1", 114 "pll2_clkctrl", "pll2"; 115 116 clocks = <&dss_dss_clk>, 117 <&dss_video1_clk>, 118 <&dss_video2_clk>; 119 clock-names = "fck", "video1_clk", "video2_clk"; 120}; 121 122&mailbox5 { 123 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { 124 ti,mbox-tx = <6 2 2>; 125 ti,mbox-rx = <4 2 2>; 126 status = "disabled"; 127 }; 128 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { 129 ti,mbox-tx = <5 2 2>; 130 ti,mbox-rx = <1 2 2>; 131 status = "disabled"; 132 }; 133}; 134 135&mailbox6 { 136 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { 137 ti,mbox-tx = <6 2 2>; 138 ti,mbox-rx = <4 2 2>; 139 status = "disabled"; 140 }; 141 mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { 142 ti,mbox-tx = <5 2 2>; 143 ti,mbox-rx = <1 2 2>; 144 status = "disabled"; 145 }; 146};
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