1/*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
--- 6 unchanged lines hidden (view full) ---
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu0: cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a15";
22 reg = <0>;
23
24 /* cooling options */
25 cooling-min-level = <0>;
26 cooling-max-level = <2>;
27 #cooling-cells = <2>; /* min followed by max */
28 };
29 };
30
31 pmu {
32 compatible = "arm,cortex-a15-pmu";
33 interrupt-parent = <&wakeupgen>;
34 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
35 };
36};
37
38&dss {
39 reg = <0x58000000 0x80>,
40 <0x58004054 0x4>,
41 <0x58004300 0x20>;
42 reg-names = "dss", "pll1_clkctrl", "pll1";
43
44 clocks = <&dss_dss_clk>,
45 <&dss_video1_clk>;
46 clock-names = "fck", "video1_clk";
47};
48
49&mailbox5 {
50 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
51 ti,mbox-tx = <6 2 2>;
52 ti,mbox-rx = <4 2 2>;
53 status = "disabled";
54 };
55 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
56 ti,mbox-tx = <5 2 2>;
57 ti,mbox-rx = <1 2 2>;
58 status = "disabled";
59 };
60};
61
62&mailbox6 {
63 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
64 ti,mbox-tx = <6 2 2>;
65 ti,mbox-rx = <4 2 2>;
66 status = "disabled";
67 };
68};
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
--- 6 unchanged lines hidden (view full) ---
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu0: cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a15";
22 reg = <0>;
23
24 /* cooling options */
25 cooling-min-level = <0>;
26 cooling-max-level = <2>;
27 #cooling-cells = <2>; /* min followed by max */
28 };
29 };
30
31 pmu {
32 compatible = "arm,cortex-a15-pmu";
33 interrupt-parent = <&wakeupgen>;
34 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
35 };
36};
37
38&dss {
39 reg = <0x58000000 0x80>,
40 <0x58004054 0x4>,
41 <0x58004300 0x20>;
42 reg-names = "dss", "pll1_clkctrl", "pll1";
43
44 clocks = <&dss_dss_clk>,
45 <&dss_video1_clk>;
46 clock-names = "fck", "video1_clk";
47};
48
49&mailbox5 {
50 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
51 ti,mbox-tx = <6 2 2>;
52 ti,mbox-rx = <4 2 2>;
53 status = "disabled";
54 };
55 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
56 ti,mbox-tx = <5 2 2>;
57 ti,mbox-rx = <1 2 2>;
58 status = "disabled";
59 };
60};
61
62&mailbox6 {
63 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
64 ti,mbox-tx = <6 2 2>;
65 ti,mbox-rx = <4 2 2>;
66 status = "disabled";
67 };
68};