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dra7-evm.dts (279385) dra7-evm.dts (295436)
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "dra74x.dtsi"
11#include <dt-bindings/gpio/gpio.h>
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "dra74x.dtsi"
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/clk/ti-dra7-atl.h>
13#include <dt-bindings/input/input.h>
12
13/ {
14 model = "TI DRA742";
15 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
16
17 memory {
18 device_type = "memory";
19 reg = <0x80000000 0x60000000>; /* 1536 MB */
20 };
21
14
15/ {
16 model = "TI DRA742";
17 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
18
19 memory {
20 device_type = "memory";
21 reg = <0x80000000 0x60000000>; /* 1536 MB */
22 };
23
22 mmc2_3v3: fixedregulator-mmc2 {
24 evm_3v3_sd: fixedregulator-sd {
23 compatible = "regulator-fixed";
25 compatible = "regulator-fixed";
24 regulator-name = "mmc2_3v3";
26 regulator-name = "evm_3v3_sd";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 enable-active-high;
30 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
27 };
28
31 };
32
33 evm_3v3_sw: fixedregulator-evm_3v3_sw {
34 compatible = "regulator-fixed";
35 regulator-name = "evm_3v3_sw";
36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>;
38 };
39
40 aic_dvdd: fixedregulator-aic_dvdd {
41 /* TPS77018DBVT */
42 compatible = "regulator-fixed";
43 regulator-name = "aic_dvdd";
44 vin-supply = <&evm_3v3_sw>;
45 regulator-min-microvolt = <1800000>;
46 regulator-max-microvolt = <1800000>;
47 };
48
29 extcon_usb1: extcon_usb1 {
30 compatible = "linux,extcon-usb-gpio";
31 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
32 };
33
34 extcon_usb2: extcon_usb2 {
35 compatible = "linux,extcon-usb-gpio";
36 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
37 };
38
39 vtt_fixed: fixedregulator-vtt {
40 compatible = "regulator-fixed";
41 regulator-name = "vtt_fixed";
42 regulator-min-microvolt = <1350000>;
43 regulator-max-microvolt = <1350000>;
44 regulator-always-on;
45 regulator-boot-on;
46 enable-active-high;
47 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
48 };
49 extcon_usb1: extcon_usb1 {
50 compatible = "linux,extcon-usb-gpio";
51 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
52 };
53
54 extcon_usb2: extcon_usb2 {
55 compatible = "linux,extcon-usb-gpio";
56 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
57 };
58
59 vtt_fixed: fixedregulator-vtt {
60 compatible = "regulator-fixed";
61 regulator-name = "vtt_fixed";
62 regulator-min-microvolt = <1350000>;
63 regulator-max-microvolt = <1350000>;
64 regulator-always-on;
65 regulator-boot-on;
66 enable-active-high;
67 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
68 };
69
70 sound0: sound@0 {
71 compatible = "simple-audio-card";
72 simple-audio-card,name = "DRA7xx-EVM";
73 simple-audio-card,widgets =
74 "Headphone", "Headphone Jack",
75 "Line", "Line Out",
76 "Microphone", "Mic Jack",
77 "Line", "Line In";
78 simple-audio-card,routing =
79 "Headphone Jack", "HPLOUT",
80 "Headphone Jack", "HPROUT",
81 "Line Out", "LLOUT",
82 "Line Out", "RLOUT",
83 "MIC3L", "Mic Jack",
84 "MIC3R", "Mic Jack",
85 "Mic Jack", "Mic Bias",
86 "LINE1L", "Line In",
87 "LINE1R", "Line In";
88 simple-audio-card,format = "dsp_b";
89 simple-audio-card,bitclock-master = <&sound0_master>;
90 simple-audio-card,frame-master = <&sound0_master>;
91 simple-audio-card,bitclock-inversion;
92
93 sound0_master: simple-audio-card,cpu {
94 sound-dai = <&mcasp3>;
95 system-clock-frequency = <5644800>;
96 };
97
98 simple-audio-card,codec {
99 sound-dai = <&tlv320aic3106>;
100 clocks = <&atl_clkin2_ck>;
101 };
102 };
103
104 leds {
105 compatible = "gpio-leds";
106 led@0 {
107 label = "dra7:usr1";
108 gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
109 default-state = "off";
110 };
111
112 led@1 {
113 label = "dra7:usr2";
114 gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
115 default-state = "off";
116 };
117
118 led@2 {
119 label = "dra7:usr3";
120 gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
121 default-state = "off";
122 };
123
124 led@3 {
125 label = "dra7:usr4";
126 gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
127 default-state = "off";
128 };
129 };
130
131 gpio_keys {
132 compatible = "gpio-keys";
133 #address-cells = <1>;
134 #size-cells = <0>;
135 autorepeat;
136
137 USER1 {
138 label = "btnUser1";
139 linux,code = <BTN_0>;
140 gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
141 };
142
143 USER2 {
144 label = "btnUser2";
145 linux,code = <BTN_1>;
146 gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
147 };
148 };
49};
50
51&dra7_pmx_core {
52 pinctrl-names = "default";
53 pinctrl-0 = <&vtt_pin>;
54
55 vtt_pin: pinmux_vtt_pin {
56 pinctrl-single,pins = <
149};
150
151&dra7_pmx_core {
152 pinctrl-names = "default";
153 pinctrl-0 = <&vtt_pin>;
154
155 vtt_pin: pinmux_vtt_pin {
156 pinctrl-single,pins = <
57 0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
157 DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
58 >;
59 };
60
61 i2c1_pins: pinmux_i2c1_pins {
62 pinctrl-single,pins = <
158 >;
159 };
160
161 i2c1_pins: pinmux_i2c1_pins {
162 pinctrl-single,pins = <
63 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
64 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
163 DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda */
164 DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl */
65 >;
66 };
67
68 i2c2_pins: pinmux_i2c2_pins {
69 pinctrl-single,pins = <
165 >;
166 };
167
168 i2c2_pins: pinmux_i2c2_pins {
169 pinctrl-single,pins = <
70 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
71 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
170 DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
171 DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
72 >;
73 };
74
75 i2c3_pins: pinmux_i2c3_pins {
76 pinctrl-single,pins = <
172 >;
173 };
174
175 i2c3_pins: pinmux_i2c3_pins {
176 pinctrl-single,pins = <
77 0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
78 0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
177 DRA7XX_CORE_IOPAD(0x3688, PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
178 DRA7XX_CORE_IOPAD(0x368c, PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
79 >;
80 };
81
82 mcspi1_pins: pinmux_mcspi1_pins {
83 pinctrl-single,pins = <
179 >;
180 };
181
182 mcspi1_pins: pinmux_mcspi1_pins {
183 pinctrl-single,pins = <
84 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
85 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
86 0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
87 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
88 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
89 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
184 DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0) /* spi1_sclk */
185 DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0) /* spi1_d1 */
186 DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0) /* spi1_d0 */
187 DRA7XX_CORE_IOPAD(0x37b0, PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
188 DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
189 DRA7XX_CORE_IOPAD(0x37bc, PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
90 >;
91 };
92
93 mcspi2_pins: pinmux_mcspi2_pins {
94 pinctrl-single,pins = <
190 >;
191 };
192
193 mcspi2_pins: pinmux_mcspi2_pins {
194 pinctrl-single,pins = <
95 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
96 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
97 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
98 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
195 DRA7XX_CORE_IOPAD(0x37c0, PIN_INPUT | MUX_MODE0) /* spi2_sclk */
196 DRA7XX_CORE_IOPAD(0x37c4, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
197 DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
198 DRA7XX_CORE_IOPAD(0x37cc, PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
99 >;
100 };
101
102 uart1_pins: pinmux_uart1_pins {
103 pinctrl-single,pins = <
199 >;
200 };
201
202 uart1_pins: pinmux_uart1_pins {
203 pinctrl-single,pins = <
104 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
105 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
106 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
107 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
204 DRA7XX_CORE_IOPAD(0x37e0, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
205 DRA7XX_CORE_IOPAD(0x37e4, PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
206 DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
207 DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
108 >;
109 };
110
111 uart2_pins: pinmux_uart2_pins {
112 pinctrl-single,pins = <
208 >;
209 };
210
211 uart2_pins: pinmux_uart2_pins {
212 pinctrl-single,pins = <
113 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
114 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
115 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
116 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
213 DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT | MUX_MODE0) /* uart2_rxd */
214 DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT | MUX_MODE0) /* uart2_txd */
215 DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
216 DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
117 >;
118 };
119
120 uart3_pins: pinmux_uart3_pins {
121 pinctrl-single,pins = <
217 >;
218 };
219
220 uart3_pins: pinmux_uart3_pins {
221 pinctrl-single,pins = <
122 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
123 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
222 DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
223 DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
124 >;
125 };
126
127 qspi1_pins: pinmux_qspi1_pins {
128 pinctrl-single,pins = <
224 >;
225 };
226
227 qspi1_pins: pinmux_qspi1_pins {
228 pinctrl-single,pins = <
129 0x4c (PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
130 0x50 (PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
131 0x74 (PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
132 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
133 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
134 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
135 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
136 0x88 (PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
137 0xb8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
138 0xbc (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
229 DRA7XX_CORE_IOPAD(0x344c, PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */
230 DRA7XX_CORE_IOPAD(0x3450, PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */
231 DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */
232 DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */
233 DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */
234 DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
235 DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */
236 DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */
237 DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */
238 DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */
139 >;
140 };
141
142 usb1_pins: pinmux_usb1_pins {
143 pinctrl-single,pins = <
239 >;
240 };
241
242 usb1_pins: pinmux_usb1_pins {
243 pinctrl-single,pins = <
144 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
244 DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
145 >;
146 };
147
148 usb2_pins: pinmux_usb2_pins {
149 pinctrl-single,pins = <
245 >;
246 };
247
248 usb2_pins: pinmux_usb2_pins {
249 pinctrl-single,pins = <
150 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
250 DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
151 >;
152 };
153
154 nand_flash_x16: nand_flash_x16 {
155 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
156 * So NAND flash requires following switch settings:
157 * SW5.9 (GPMC_WPN) = LOW
158 * SW5.1 (NAND_BOOTn) = HIGH */
159 pinctrl-single,pins = <
251 >;
252 };
253
254 nand_flash_x16: nand_flash_x16 {
255 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
256 * So NAND flash requires following switch settings:
257 * SW5.9 (GPMC_WPN) = LOW
258 * SW5.1 (NAND_BOOTn) = HIGH */
259 pinctrl-single,pins = <
160 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
161 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
162 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
163 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
164 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
165 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
166 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
167 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
168 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
169 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
170 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
171 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
172 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
173 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
174 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
175 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
176 0xd8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
177 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
178 0xb4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
179 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
180 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
181 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
260 DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */
261 DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */
262 DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */
263 DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */
264 DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */
265 DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */
266 DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */
267 DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */
268 DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */
269 DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */
270 DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */
271 DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */
272 DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */
273 DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */
274 DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */
275 DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */
276 DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0 */
277 DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */
278 DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0 */
279 DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */
280 DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */
281 DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */
182 >;
183 };
184
185 cpsw_default: cpsw_default {
186 pinctrl-single,pins = <
187 /* Slave 1 */
282 >;
283 };
284
285 cpsw_default: cpsw_default {
286 pinctrl-single,pins = <
287 /* Slave 1 */
188 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
189 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
190 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
191 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
192 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
193 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
194 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
195 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
196 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
197 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
198 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
199 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
288 DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */
289 DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */
290 DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */
291 DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */
292 DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */
293 DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */
294 DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */
295 DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */
296 DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */
297 DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */
298 DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */
299 DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */
200
201 /* Slave 2 */
300
301 /* Slave 2 */
202 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
203 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
204 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
205 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
206 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
207 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
208 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
209 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
210 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
211 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
212 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
213 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
302 DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */
303 DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */
304 DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */
305 DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */
306 DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */
307 DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */
308 DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */
309 DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */
310 DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */
311 DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */
312 DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */
313 DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */
214 >;
215
216 };
217
218 cpsw_sleep: cpsw_sleep {
219 pinctrl-single,pins = <
220 /* Slave 1 */
314 >;
315
316 };
317
318 cpsw_sleep: cpsw_sleep {
319 pinctrl-single,pins = <
320 /* Slave 1 */
221 0x250 (MUX_MODE15)
222 0x254 (MUX_MODE15)
223 0x258 (MUX_MODE15)
224 0x25c (MUX_MODE15)
225 0x260 (MUX_MODE15)
226 0x264 (MUX_MODE15)
227 0x268 (MUX_MODE15)
228 0x26c (MUX_MODE15)
229 0x270 (MUX_MODE15)
230 0x274 (MUX_MODE15)
231 0x278 (MUX_MODE15)
232 0x27c (MUX_MODE15)
321 DRA7XX_CORE_IOPAD(0x3650, MUX_MODE15)
322 DRA7XX_CORE_IOPAD(0x3654, MUX_MODE15)
323 DRA7XX_CORE_IOPAD(0x3658, MUX_MODE15)
324 DRA7XX_CORE_IOPAD(0x365c, MUX_MODE15)
325 DRA7XX_CORE_IOPAD(0x3660, MUX_MODE15)
326 DRA7XX_CORE_IOPAD(0x3664, MUX_MODE15)
327 DRA7XX_CORE_IOPAD(0x3668, MUX_MODE15)
328 DRA7XX_CORE_IOPAD(0x366c, MUX_MODE15)
329 DRA7XX_CORE_IOPAD(0x3670, MUX_MODE15)
330 DRA7XX_CORE_IOPAD(0x3674, MUX_MODE15)
331 DRA7XX_CORE_IOPAD(0x3678, MUX_MODE15)
332 DRA7XX_CORE_IOPAD(0x367c, MUX_MODE15)
233
234 /* Slave 2 */
333
334 /* Slave 2 */
235 0x198 (MUX_MODE15)
236 0x19c (MUX_MODE15)
237 0x1a0 (MUX_MODE15)
238 0x1a4 (MUX_MODE15)
239 0x1a8 (MUX_MODE15)
240 0x1ac (MUX_MODE15)
241 0x1b0 (MUX_MODE15)
242 0x1b4 (MUX_MODE15)
243 0x1b8 (MUX_MODE15)
244 0x1bc (MUX_MODE15)
245 0x1c0 (MUX_MODE15)
246 0x1c4 (MUX_MODE15)
335 DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15)
336 DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15)
337 DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15)
338 DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15)
339 DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15)
340 DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15)
341 DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15)
342 DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15)
343 DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15)
344 DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15)
345 DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15)
346 DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15)
247 >;
248 };
249
250 davinci_mdio_default: davinci_mdio_default {
251 pinctrl-single,pins = <
347 >;
348 };
349
350 davinci_mdio_default: davinci_mdio_default {
351 pinctrl-single,pins = <
252 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
253 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
352 DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */
353 DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
254 >;
255 };
256
257 davinci_mdio_sleep: davinci_mdio_sleep {
258 pinctrl-single,pins = <
354 >;
355 };
356
357 davinci_mdio_sleep: davinci_mdio_sleep {
358 pinctrl-single,pins = <
259 0x23c (MUX_MODE15)
260 0x240 (MUX_MODE15)
359 DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15)
360 DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15)
261 >;
262 };
263
264 dcan1_pins_default: dcan1_pins_default {
265 pinctrl-single,pins = <
361 >;
362 };
363
364 dcan1_pins_default: dcan1_pins_default {
365 pinctrl-single,pins = <
266 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */
267 0x3d4 (MUX_MODE15) /* dcan1_rx.off */
268 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */
366 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
367 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
269 >;
270 };
271
272 dcan1_pins_sleep: dcan1_pins_sleep {
273 pinctrl-single,pins = <
368 >;
369 };
370
371 dcan1_pins_sleep: dcan1_pins_sleep {
372 pinctrl-single,pins = <
274 0x3d0 (MUX_MODE15) /* dcan1_tx.off */
275 0x3d4 (MUX_MODE15) /* dcan1_rx.off */
276 0x418 (MUX_MODE15) /* wakeup0.off */
373 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
374 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
277 >;
278 };
375 >;
376 };
377
378 atl_pins: pinmux_atl_pins {
379 pinctrl-single,pins = <
380 DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */
381 DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */
382 >;
383 };
384
385 mcasp3_pins: pinmux_mcasp3_pins {
386 pinctrl-single,pins = <
387 DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */
388 DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */
389 DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */
390 DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */
391 >;
392 };
393
394 mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins {
395 pinctrl-single,pins = <
396 DRA7XX_CORE_IOPAD(0x3724, MUX_MODE15)
397 DRA7XX_CORE_IOPAD(0x3728, MUX_MODE15)
398 DRA7XX_CORE_IOPAD(0x372c, MUX_MODE15)
399 DRA7XX_CORE_IOPAD(0x3730, MUX_MODE15)
400 >;
401 };
279};
280
281&i2c1 {
282 status = "okay";
283 pinctrl-names = "default";
284 pinctrl-0 = <&i2c1_pins>;
285 clock-frequency = <400000>;
286
287 tps659038: tps659038@58 {
288 compatible = "ti,tps659038";
289 reg = <0x58>;
290
291 tps659038_pmic {
292 compatible = "ti,tps659038-pmic";
293
294 regulators {
295 smps123_reg: smps123 {
296 /* VDD_MPU */
297 regulator-name = "smps123";
298 regulator-min-microvolt = < 850000>;
299 regulator-max-microvolt = <1250000>;
300 regulator-always-on;
301 regulator-boot-on;
302 };
303
304 smps45_reg: smps45 {
305 /* VDD_DSPEVE */
306 regulator-name = "smps45";
307 regulator-min-microvolt = < 850000>;
308 regulator-max-microvolt = <1150000>;
309 regulator-always-on;
310 regulator-boot-on;
311 };
312
313 smps6_reg: smps6 {
314 /* VDD_GPU - over VDD_SMPS6 */
315 regulator-name = "smps6";
316 regulator-min-microvolt = <850000>;
317 regulator-max-microvolt = <1250000>;
318 regulator-always-on;
319 regulator-boot-on;
320 };
321
322 smps7_reg: smps7 {
323 /* CORE_VDD */
324 regulator-name = "smps7";
325 regulator-min-microvolt = <850000>;
326 regulator-max-microvolt = <1060000>;
327 regulator-always-on;
328 regulator-boot-on;
329 };
330
331 smps8_reg: smps8 {
332 /* VDD_IVAHD */
333 regulator-name = "smps8";
334 regulator-min-microvolt = < 850000>;
335 regulator-max-microvolt = <1250000>;
336 regulator-always-on;
337 regulator-boot-on;
338 };
339
340 smps9_reg: smps9 {
341 /* VDDS1V8 */
342 regulator-name = "smps9";
343 regulator-min-microvolt = <1800000>;
344 regulator-max-microvolt = <1800000>;
345 regulator-always-on;
346 regulator-boot-on;
347 };
348
349 ldo1_reg: ldo1 {
350 /* LDO1_OUT --> SDIO */
351 regulator-name = "ldo1";
352 regulator-min-microvolt = <1800000>;
353 regulator-max-microvolt = <3300000>;
402};
403
404&i2c1 {
405 status = "okay";
406 pinctrl-names = "default";
407 pinctrl-0 = <&i2c1_pins>;
408 clock-frequency = <400000>;
409
410 tps659038: tps659038@58 {
411 compatible = "ti,tps659038";
412 reg = <0x58>;
413
414 tps659038_pmic {
415 compatible = "ti,tps659038-pmic";
416
417 regulators {
418 smps123_reg: smps123 {
419 /* VDD_MPU */
420 regulator-name = "smps123";
421 regulator-min-microvolt = < 850000>;
422 regulator-max-microvolt = <1250000>;
423 regulator-always-on;
424 regulator-boot-on;
425 };
426
427 smps45_reg: smps45 {
428 /* VDD_DSPEVE */
429 regulator-name = "smps45";
430 regulator-min-microvolt = < 850000>;
431 regulator-max-microvolt = <1150000>;
432 regulator-always-on;
433 regulator-boot-on;
434 };
435
436 smps6_reg: smps6 {
437 /* VDD_GPU - over VDD_SMPS6 */
438 regulator-name = "smps6";
439 regulator-min-microvolt = <850000>;
440 regulator-max-microvolt = <1250000>;
441 regulator-always-on;
442 regulator-boot-on;
443 };
444
445 smps7_reg: smps7 {
446 /* CORE_VDD */
447 regulator-name = "smps7";
448 regulator-min-microvolt = <850000>;
449 regulator-max-microvolt = <1060000>;
450 regulator-always-on;
451 regulator-boot-on;
452 };
453
454 smps8_reg: smps8 {
455 /* VDD_IVAHD */
456 regulator-name = "smps8";
457 regulator-min-microvolt = < 850000>;
458 regulator-max-microvolt = <1250000>;
459 regulator-always-on;
460 regulator-boot-on;
461 };
462
463 smps9_reg: smps9 {
464 /* VDDS1V8 */
465 regulator-name = "smps9";
466 regulator-min-microvolt = <1800000>;
467 regulator-max-microvolt = <1800000>;
468 regulator-always-on;
469 regulator-boot-on;
470 };
471
472 ldo1_reg: ldo1 {
473 /* LDO1_OUT --> SDIO */
474 regulator-name = "ldo1";
475 regulator-min-microvolt = <1800000>;
476 regulator-max-microvolt = <3300000>;
477 regulator-always-on;
354 regulator-boot-on;
355 };
356
357 ldo2_reg: ldo2 {
358 /* VDD_RTCIO */
359 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
360 regulator-name = "ldo2";
361 regulator-min-microvolt = <3300000>;
362 regulator-max-microvolt = <3300000>;
363 regulator-always-on;
364 regulator-boot-on;
365 };
366
367 ldo3_reg: ldo3 {
368 /* VDDA_1V8_PHY */
369 regulator-name = "ldo3";
370 regulator-min-microvolt = <1800000>;
371 regulator-max-microvolt = <1800000>;
372 regulator-always-on;
373 regulator-boot-on;
374 };
375
376 ldo9_reg: ldo9 {
377 /* VDD_RTC */
378 regulator-name = "ldo9";
379 regulator-min-microvolt = <1050000>;
380 regulator-max-microvolt = <1050000>;
381 regulator-always-on;
382 regulator-boot-on;
478 regulator-boot-on;
479 };
480
481 ldo2_reg: ldo2 {
482 /* VDD_RTCIO */
483 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
484 regulator-name = "ldo2";
485 regulator-min-microvolt = <3300000>;
486 regulator-max-microvolt = <3300000>;
487 regulator-always-on;
488 regulator-boot-on;
489 };
490
491 ldo3_reg: ldo3 {
492 /* VDDA_1V8_PHY */
493 regulator-name = "ldo3";
494 regulator-min-microvolt = <1800000>;
495 regulator-max-microvolt = <1800000>;
496 regulator-always-on;
497 regulator-boot-on;
498 };
499
500 ldo9_reg: ldo9 {
501 /* VDD_RTC */
502 regulator-name = "ldo9";
503 regulator-min-microvolt = <1050000>;
504 regulator-max-microvolt = <1050000>;
505 regulator-always-on;
506 regulator-boot-on;
507 regulator-allow-bypass;
383 };
384
385 ldoln_reg: ldoln {
386 /* VDDA_1V8_PLL */
387 regulator-name = "ldoln";
388 regulator-min-microvolt = <1800000>;
389 regulator-max-microvolt = <1800000>;
390 regulator-always-on;
391 regulator-boot-on;
392 };
393
394 ldousb_reg: ldousb {
395 /* VDDA_3V_USB: VDDA_USBHS33 */
396 regulator-name = "ldousb";
397 regulator-min-microvolt = <3300000>;
398 regulator-max-microvolt = <3300000>;
399 regulator-boot-on;
400 };
401 };
402 };
403 };
404
508 };
509
510 ldoln_reg: ldoln {
511 /* VDDA_1V8_PLL */
512 regulator-name = "ldoln";
513 regulator-min-microvolt = <1800000>;
514 regulator-max-microvolt = <1800000>;
515 regulator-always-on;
516 regulator-boot-on;
517 };
518
519 ldousb_reg: ldousb {
520 /* VDDA_3V_USB: VDDA_USBHS33 */
521 regulator-name = "ldousb";
522 regulator-min-microvolt = <3300000>;
523 regulator-max-microvolt = <3300000>;
524 regulator-boot-on;
525 };
526 };
527 };
528 };
529
530 pcf_lcd: gpio@20 {
531 compatible = "nxp,pcf8575";
532 reg = <0x20>;
533 gpio-controller;
534 #gpio-cells = <2>;
535 interrupt-parent = <&gpio6>;
536 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
537 interrupt-controller;
538 #interrupt-cells = <2>;
539 };
540
405 pcf_gpio_21: gpio@21 {
406 compatible = "ti,pcf8575";
407 reg = <0x21>;
408 lines-initial-states = <0x1408>;
409 gpio-controller;
410 #gpio-cells = <2>;
411 interrupt-parent = <&gpio6>;
412 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
413 interrupt-controller;
414 #interrupt-cells = <2>;
415 };
416
541 pcf_gpio_21: gpio@21 {
542 compatible = "ti,pcf8575";
543 reg = <0x21>;
544 lines-initial-states = <0x1408>;
545 gpio-controller;
546 #gpio-cells = <2>;
547 interrupt-parent = <&gpio6>;
548 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
549 interrupt-controller;
550 #interrupt-cells = <2>;
551 };
552
553 tlv320aic3106: tlv320aic3106@19 {
554 #sound-dai-cells = <0>;
555 compatible = "ti,tlv320aic3106";
556 reg = <0x19>;
557 adc-settle-ms = <40>;
558 ai3x-micbias-vg = <1>; /* 2.0V */
559 status = "okay";
560
561 /* Regulators */
562 AVDD-supply = <&evm_3v3_sw>;
563 IOVDD-supply = <&evm_3v3_sw>;
564 DRVDD-supply = <&evm_3v3_sw>;
565 DVDD-supply = <&aic_dvdd>;
566 };
417};
418
419&i2c2 {
420 status = "okay";
421 pinctrl-names = "default";
422 pinctrl-0 = <&i2c2_pins>;
423 clock-frequency = <400000>;
567};
568
569&i2c2 {
570 status = "okay";
571 pinctrl-names = "default";
572 pinctrl-0 = <&i2c2_pins>;
573 clock-frequency = <400000>;
574
575 pcf_hdmi: gpio@26 {
576 compatible = "nxp,pcf8575";
577 reg = <0x26>;
578 gpio-controller;
579 #gpio-cells = <2>;
580 p1 {
581 /* vin6_sel_s0: high: VIN6, low: audio */
582 gpio-hog;
583 gpios = <1 GPIO_ACTIVE_HIGH>;
584 output-low;
585 line-name = "vin6_sel_s0";
586 };
587 };
424};
425
426&i2c3 {
427 status = "okay";
428 pinctrl-names = "default";
429 pinctrl-0 = <&i2c3_pins>;
430 clock-frequency = <400000>;
431};
432
433&mcspi1 {
434 status = "okay";
435 pinctrl-names = "default";
436 pinctrl-0 = <&mcspi1_pins>;
437};
438
439&mcspi2 {
440 status = "okay";
441 pinctrl-names = "default";
442 pinctrl-0 = <&mcspi2_pins>;
443};
444
445&uart1 {
446 status = "okay";
447 pinctrl-names = "default";
448 pinctrl-0 = <&uart1_pins>;
588};
589
590&i2c3 {
591 status = "okay";
592 pinctrl-names = "default";
593 pinctrl-0 = <&i2c3_pins>;
594 clock-frequency = <400000>;
595};
596
597&mcspi1 {
598 status = "okay";
599 pinctrl-names = "default";
600 pinctrl-0 = <&mcspi1_pins>;
601};
602
603&mcspi2 {
604 status = "okay";
605 pinctrl-names = "default";
606 pinctrl-0 = <&mcspi2_pins>;
607};
608
609&uart1 {
610 status = "okay";
611 pinctrl-names = "default";
612 pinctrl-0 = <&uart1_pins>;
449 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
613 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
450 <&dra7_pmx_core 0x3e0>;
451};
452
453&uart2 {
454 status = "okay";
455 pinctrl-names = "default";
456 pinctrl-0 = <&uart2_pins>;
457};
458
459&uart3 {
460 status = "okay";
461 pinctrl-names = "default";
462 pinctrl-0 = <&uart3_pins>;
463};
464
465&mmc1 {
466 status = "okay";
614 <&dra7_pmx_core 0x3e0>;
615};
616
617&uart2 {
618 status = "okay";
619 pinctrl-names = "default";
620 pinctrl-0 = <&uart2_pins>;
621};
622
623&uart3 {
624 status = "okay";
625 pinctrl-names = "default";
626 pinctrl-0 = <&uart3_pins>;
627};
628
629&mmc1 {
630 status = "okay";
467 vmmc-supply = <&ldo1_reg>;
631 vmmc-supply = <&evm_3v3_sd>;
632 vmmc_aux-supply = <&ldo1_reg>;
468 bus-width = <4>;
633 bus-width = <4>;
634 /*
635 * SDCD signal is not being used here - using the fact that GPIO mode
636 * is always hardwired.
637 */
638 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
469};
470
471&mmc2 {
472 status = "okay";
639};
640
641&mmc2 {
642 status = "okay";
473 vmmc-supply = <&mmc2_3v3>;
643 vmmc-supply = <&evm_3v3_sw>;
474 bus-width = <8>;
475};
476
477&cpu0 {
478 cpu0-supply = <&smps123_reg>;
479};
480
481&qspi {
482 status = "okay";
483 pinctrl-names = "default";
484 pinctrl-0 = <&qspi1_pins>;
485
486 spi-max-frequency = <48000000>;
487 m25p80@0 {
488 compatible = "s25fl256s1";
489 spi-max-frequency = <48000000>;
490 reg = <0>;
491 spi-tx-bus-width = <1>;
492 spi-rx-bus-width = <4>;
493 spi-cpol;
494 spi-cpha;
495 #address-cells = <1>;
496 #size-cells = <1>;
497
498 /* MTD partition table.
499 * The ROM checks the first four physical blocks
500 * for a valid file to boot and the flash here is
501 * 64KiB block size.
502 */
503 partition@0 {
504 label = "QSPI.SPL";
505 reg = <0x00000000 0x000010000>;
506 };
507 partition@1 {
508 label = "QSPI.SPL.backup1";
509 reg = <0x00010000 0x00010000>;
510 };
511 partition@2 {
512 label = "QSPI.SPL.backup2";
513 reg = <0x00020000 0x00010000>;
514 };
515 partition@3 {
516 label = "QSPI.SPL.backup3";
517 reg = <0x00030000 0x00010000>;
518 };
519 partition@4 {
520 label = "QSPI.u-boot";
521 reg = <0x00040000 0x00100000>;
522 };
523 partition@5 {
524 label = "QSPI.u-boot-spl-os";
525 reg = <0x00140000 0x00080000>;
526 };
527 partition@6 {
528 label = "QSPI.u-boot-env";
529 reg = <0x001c0000 0x00010000>;
530 };
531 partition@7 {
532 label = "QSPI.u-boot-env.backup1";
533 reg = <0x001d0000 0x0010000>;
534 };
535 partition@8 {
536 label = "QSPI.kernel";
537 reg = <0x001e0000 0x0800000>;
538 };
539 partition@9 {
540 label = "QSPI.file-system";
541 reg = <0x009e0000 0x01620000>;
542 };
543 };
544};
545
546&omap_dwc3_1 {
547 extcon = <&extcon_usb1>;
548};
549
550&omap_dwc3_2 {
551 extcon = <&extcon_usb2>;
552};
553
554&usb1 {
555 dr_mode = "peripheral";
556 pinctrl-names = "default";
557 pinctrl-0 = <&usb1_pins>;
558};
559
560&usb2 {
561 dr_mode = "host";
562 pinctrl-names = "default";
563 pinctrl-0 = <&usb2_pins>;
564};
565
566&elm {
567 status = "okay";
568};
569
570&gpmc {
571 status = "okay";
572 pinctrl-names = "default";
573 pinctrl-0 = <&nand_flash_x16>;
574 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
575 nand@0,0 {
576 reg = <0 0 4>; /* device IO registers */
577 ti,nand-ecc-opt = "bch8";
578 ti,elm-id = <&elm>;
579 nand-bus-width = <16>;
580 gpmc,device-width = <2>;
581 gpmc,sync-clk-ps = <0>;
582 gpmc,cs-on-ns = <0>;
583 gpmc,cs-rd-off-ns = <80>;
584 gpmc,cs-wr-off-ns = <80>;
585 gpmc,adv-on-ns = <0>;
586 gpmc,adv-rd-off-ns = <60>;
587 gpmc,adv-wr-off-ns = <60>;
588 gpmc,we-on-ns = <10>;
589 gpmc,we-off-ns = <50>;
590 gpmc,oe-on-ns = <4>;
591 gpmc,oe-off-ns = <40>;
592 gpmc,access-ns = <40>;
593 gpmc,wr-access-ns = <80>;
594 gpmc,rd-cycle-ns = <80>;
595 gpmc,wr-cycle-ns = <80>;
596 gpmc,bus-turnaround-ns = <0>;
597 gpmc,cycle2cycle-delay-ns = <0>;
598 gpmc,clk-activation-ns = <0>;
599 gpmc,wait-monitoring-ns = <0>;
600 gpmc,wr-data-mux-bus-ns = <0>;
601 /* MTD partition table */
602 /* All SPL-* partitions are sized to minimal length
603 * which can be independently programmable. For
604 * NAND flash this is equal to size of erase-block */
605 #address-cells = <1>;
606 #size-cells = <1>;
607 partition@0 {
608 label = "NAND.SPL";
609 reg = <0x00000000 0x000020000>;
610 };
611 partition@1 {
612 label = "NAND.SPL.backup1";
613 reg = <0x00020000 0x00020000>;
614 };
615 partition@2 {
616 label = "NAND.SPL.backup2";
617 reg = <0x00040000 0x00020000>;
618 };
619 partition@3 {
620 label = "NAND.SPL.backup3";
621 reg = <0x00060000 0x00020000>;
622 };
623 partition@4 {
624 label = "NAND.u-boot-spl-os";
625 reg = <0x00080000 0x00040000>;
626 };
627 partition@5 {
628 label = "NAND.u-boot";
629 reg = <0x000c0000 0x00100000>;
630 };
631 partition@6 {
632 label = "NAND.u-boot-env";
633 reg = <0x001c0000 0x00020000>;
634 };
635 partition@7 {
636 label = "NAND.u-boot-env.backup1";
637 reg = <0x001e0000 0x00020000>;
638 };
639 partition@8 {
640 label = "NAND.kernel";
641 reg = <0x00200000 0x00800000>;
642 };
643 partition@9 {
644 label = "NAND.file-system";
645 reg = <0x00a00000 0x0f600000>;
646 };
647 };
648};
649
650&usb2_phy1 {
651 phy-supply = <&ldousb_reg>;
652};
653
654&usb2_phy2 {
655 phy-supply = <&ldousb_reg>;
656};
657
658&gpio7 {
659 ti,no-reset-on-init;
660 ti,no-idle-on-init;
661};
662
663&mac {
664 status = "okay";
665 pinctrl-names = "default", "sleep";
666 pinctrl-0 = <&cpsw_default>;
667 pinctrl-1 = <&cpsw_sleep>;
668 dual_emac;
669};
670
671&cpsw_emac0 {
672 phy_id = <&davinci_mdio>, <2>;
673 phy-mode = "rgmii";
674 dual_emac_res_vlan = <1>;
675};
676
677&cpsw_emac1 {
678 phy_id = <&davinci_mdio>, <3>;
679 phy-mode = "rgmii";
680 dual_emac_res_vlan = <2>;
681};
682
683&davinci_mdio {
684 pinctrl-names = "default", "sleep";
685 pinctrl-0 = <&davinci_mdio_default>;
686 pinctrl-1 = <&davinci_mdio_sleep>;
687};
688
689&dcan1 {
690 status = "ok";
644 bus-width = <8>;
645};
646
647&cpu0 {
648 cpu0-supply = <&smps123_reg>;
649};
650
651&qspi {
652 status = "okay";
653 pinctrl-names = "default";
654 pinctrl-0 = <&qspi1_pins>;
655
656 spi-max-frequency = <48000000>;
657 m25p80@0 {
658 compatible = "s25fl256s1";
659 spi-max-frequency = <48000000>;
660 reg = <0>;
661 spi-tx-bus-width = <1>;
662 spi-rx-bus-width = <4>;
663 spi-cpol;
664 spi-cpha;
665 #address-cells = <1>;
666 #size-cells = <1>;
667
668 /* MTD partition table.
669 * The ROM checks the first four physical blocks
670 * for a valid file to boot and the flash here is
671 * 64KiB block size.
672 */
673 partition@0 {
674 label = "QSPI.SPL";
675 reg = <0x00000000 0x000010000>;
676 };
677 partition@1 {
678 label = "QSPI.SPL.backup1";
679 reg = <0x00010000 0x00010000>;
680 };
681 partition@2 {
682 label = "QSPI.SPL.backup2";
683 reg = <0x00020000 0x00010000>;
684 };
685 partition@3 {
686 label = "QSPI.SPL.backup3";
687 reg = <0x00030000 0x00010000>;
688 };
689 partition@4 {
690 label = "QSPI.u-boot";
691 reg = <0x00040000 0x00100000>;
692 };
693 partition@5 {
694 label = "QSPI.u-boot-spl-os";
695 reg = <0x00140000 0x00080000>;
696 };
697 partition@6 {
698 label = "QSPI.u-boot-env";
699 reg = <0x001c0000 0x00010000>;
700 };
701 partition@7 {
702 label = "QSPI.u-boot-env.backup1";
703 reg = <0x001d0000 0x0010000>;
704 };
705 partition@8 {
706 label = "QSPI.kernel";
707 reg = <0x001e0000 0x0800000>;
708 };
709 partition@9 {
710 label = "QSPI.file-system";
711 reg = <0x009e0000 0x01620000>;
712 };
713 };
714};
715
716&omap_dwc3_1 {
717 extcon = <&extcon_usb1>;
718};
719
720&omap_dwc3_2 {
721 extcon = <&extcon_usb2>;
722};
723
724&usb1 {
725 dr_mode = "peripheral";
726 pinctrl-names = "default";
727 pinctrl-0 = <&usb1_pins>;
728};
729
730&usb2 {
731 dr_mode = "host";
732 pinctrl-names = "default";
733 pinctrl-0 = <&usb2_pins>;
734};
735
736&elm {
737 status = "okay";
738};
739
740&gpmc {
741 status = "okay";
742 pinctrl-names = "default";
743 pinctrl-0 = <&nand_flash_x16>;
744 ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
745 nand@0,0 {
746 reg = <0 0 4>; /* device IO registers */
747 ti,nand-ecc-opt = "bch8";
748 ti,elm-id = <&elm>;
749 nand-bus-width = <16>;
750 gpmc,device-width = <2>;
751 gpmc,sync-clk-ps = <0>;
752 gpmc,cs-on-ns = <0>;
753 gpmc,cs-rd-off-ns = <80>;
754 gpmc,cs-wr-off-ns = <80>;
755 gpmc,adv-on-ns = <0>;
756 gpmc,adv-rd-off-ns = <60>;
757 gpmc,adv-wr-off-ns = <60>;
758 gpmc,we-on-ns = <10>;
759 gpmc,we-off-ns = <50>;
760 gpmc,oe-on-ns = <4>;
761 gpmc,oe-off-ns = <40>;
762 gpmc,access-ns = <40>;
763 gpmc,wr-access-ns = <80>;
764 gpmc,rd-cycle-ns = <80>;
765 gpmc,wr-cycle-ns = <80>;
766 gpmc,bus-turnaround-ns = <0>;
767 gpmc,cycle2cycle-delay-ns = <0>;
768 gpmc,clk-activation-ns = <0>;
769 gpmc,wait-monitoring-ns = <0>;
770 gpmc,wr-data-mux-bus-ns = <0>;
771 /* MTD partition table */
772 /* All SPL-* partitions are sized to minimal length
773 * which can be independently programmable. For
774 * NAND flash this is equal to size of erase-block */
775 #address-cells = <1>;
776 #size-cells = <1>;
777 partition@0 {
778 label = "NAND.SPL";
779 reg = <0x00000000 0x000020000>;
780 };
781 partition@1 {
782 label = "NAND.SPL.backup1";
783 reg = <0x00020000 0x00020000>;
784 };
785 partition@2 {
786 label = "NAND.SPL.backup2";
787 reg = <0x00040000 0x00020000>;
788 };
789 partition@3 {
790 label = "NAND.SPL.backup3";
791 reg = <0x00060000 0x00020000>;
792 };
793 partition@4 {
794 label = "NAND.u-boot-spl-os";
795 reg = <0x00080000 0x00040000>;
796 };
797 partition@5 {
798 label = "NAND.u-boot";
799 reg = <0x000c0000 0x00100000>;
800 };
801 partition@6 {
802 label = "NAND.u-boot-env";
803 reg = <0x001c0000 0x00020000>;
804 };
805 partition@7 {
806 label = "NAND.u-boot-env.backup1";
807 reg = <0x001e0000 0x00020000>;
808 };
809 partition@8 {
810 label = "NAND.kernel";
811 reg = <0x00200000 0x00800000>;
812 };
813 partition@9 {
814 label = "NAND.file-system";
815 reg = <0x00a00000 0x0f600000>;
816 };
817 };
818};
819
820&usb2_phy1 {
821 phy-supply = <&ldousb_reg>;
822};
823
824&usb2_phy2 {
825 phy-supply = <&ldousb_reg>;
826};
827
828&gpio7 {
829 ti,no-reset-on-init;
830 ti,no-idle-on-init;
831};
832
833&mac {
834 status = "okay";
835 pinctrl-names = "default", "sleep";
836 pinctrl-0 = <&cpsw_default>;
837 pinctrl-1 = <&cpsw_sleep>;
838 dual_emac;
839};
840
841&cpsw_emac0 {
842 phy_id = <&davinci_mdio>, <2>;
843 phy-mode = "rgmii";
844 dual_emac_res_vlan = <1>;
845};
846
847&cpsw_emac1 {
848 phy_id = <&davinci_mdio>, <3>;
849 phy-mode = "rgmii";
850 dual_emac_res_vlan = <2>;
851};
852
853&davinci_mdio {
854 pinctrl-names = "default", "sleep";
855 pinctrl-0 = <&davinci_mdio_default>;
856 pinctrl-1 = <&davinci_mdio_sleep>;
857};
858
859&dcan1 {
860 status = "ok";
691 pinctrl-names = "default", "sleep";
692 pinctrl-0 = <&dcan1_pins_default>;
861 pinctrl-names = "default", "sleep", "active";
862 pinctrl-0 = <&dcan1_pins_sleep>;
693 pinctrl-1 = <&dcan1_pins_sleep>;
863 pinctrl-1 = <&dcan1_pins_sleep>;
864 pinctrl-2 = <&dcan1_pins_default>;
694};
865};
866
867&atl {
868 pinctrl-names = "default";
869 pinctrl-0 = <&atl_pins>;
870
871 assigned-clocks = <&abe_dpll_sys_clk_mux>,
872 <&atl_gfclk_mux>,
873 <&dpll_abe_ck>,
874 <&dpll_abe_m2x2_ck>,
875 <&atl_clkin2_ck>;
876 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
877 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
878
879 status = "okay";
880
881 atl2 {
882 bws = <DRA7_ATL_WS_MCASP2_FSX>;
883 aws = <DRA7_ATL_WS_MCASP3_FSX>;
884 };
885};
886
887&mcasp3 {
888 #sound-dai-cells = <0>;
889 pinctrl-names = "default", "sleep";
890 pinctrl-0 = <&mcasp3_pins>;
891 pinctrl-1 = <&mcasp3_sleep_pins>;
892
893 assigned-clocks = <&mcasp3_ahclkx_mux>;
894 assigned-clock-parents = <&atl_clkin2_ck>;
895
896 status = "okay";
897
898 op-mode = <0>; /* MCASP_IIS_MODE */
899 tdm-slots = <2>;
900 /* 4 serializer */
901 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
902 1 2 0 0
903 >;
904};
905
906&mailbox5 {
907 status = "okay";
908 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
909 status = "okay";
910 };
911 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
912 status = "okay";
913 };
914};
915
916&mailbox6 {
917 status = "okay";
918 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
919 status = "okay";
920 };
921 mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
922 status = "okay";
923 };
924};