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dm816x.dtsi (279385) dm816x.dtsi (295436)
1/*
2 * This file is licensed under the terms of the GNU General Public License
3 * version 2. This program is licensed "as is" without any warranty of any
4 * kind, whether express or implied.
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/pinctrl/omap.h>
9
10#include "skeleton.dtsi"
11
12/ {
13 compatible = "ti,dm816";
14 interrupt-parent = <&intc>;
15
16 aliases {
17 i2c0 = &i2c1;
18 i2c1 = &i2c2;
19 serial0 = &uart1;
20 serial1 = &uart2;
21 serial2 = &uart3;
22 ethernet0 = &eth0;
23 ethernet1 = &eth1;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29 cpu@0 {
30 compatible = "arm,cortex-a8";
31 device_type = "cpu";
32 reg = <0>;
33 };
34 };
35
36 pmu {
37 compatible = "arm,cortex-a8-pmu";
38 interrupts = <3>;
39 };
40
41 /*
42 * The soc node represents the soc top level view. It is used for IPs
43 * that are not memory mapped in the MPU view or for the MPU itself.
44 */
45 soc {
46 compatible = "ti,omap-infra";
47 mpu {
48 compatible = "ti,omap3-mpu";
49 ti,hwmods = "mpu";
50 };
51 };
52
53 /*
54 * XXX: Use a flat representation of the dm816x interconnect.
55 * The real dm816x interconnect network is quite complex. Since
56 * it will not bring real advantage to represent that in DT
57 * for the moment, just use a fake OCP bus entry to represent
58 * the whole bus hierarchy.
59 */
60 ocp {
1/*
2 * This file is licensed under the terms of the GNU General Public License
3 * version 2. This program is licensed "as is" without any warranty of any
4 * kind, whether express or implied.
5 */
6
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/pinctrl/omap.h>
9
10#include "skeleton.dtsi"
11
12/ {
13 compatible = "ti,dm816";
14 interrupt-parent = <&intc>;
15
16 aliases {
17 i2c0 = &i2c1;
18 i2c1 = &i2c2;
19 serial0 = &uart1;
20 serial1 = &uart2;
21 serial2 = &uart3;
22 ethernet0 = &eth0;
23 ethernet1 = &eth1;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29 cpu@0 {
30 compatible = "arm,cortex-a8";
31 device_type = "cpu";
32 reg = <0>;
33 };
34 };
35
36 pmu {
37 compatible = "arm,cortex-a8-pmu";
38 interrupts = <3>;
39 };
40
41 /*
42 * The soc node represents the soc top level view. It is used for IPs
43 * that are not memory mapped in the MPU view or for the MPU itself.
44 */
45 soc {
46 compatible = "ti,omap-infra";
47 mpu {
48 compatible = "ti,omap3-mpu";
49 ti,hwmods = "mpu";
50 };
51 };
52
53 /*
54 * XXX: Use a flat representation of the dm816x interconnect.
55 * The real dm816x interconnect network is quite complex. Since
56 * it will not bring real advantage to represent that in DT
57 * for the moment, just use a fake OCP bus entry to represent
58 * the whole bus hierarchy.
59 */
60 ocp {
61 compatible = "ti,omap3-l3-smx", "simple-bus";
61 compatible = "simple-bus";
62 reg = <0x44000000 0x10000>;
63 interrupts = <9 10>;
64 #address-cells = <1>;
65 #size-cells = <1>;
66 ranges;
62 reg = <0x44000000 0x10000>;
63 interrupts = <9 10>;
64 #address-cells = <1>;
65 #size-cells = <1>;
66 ranges;
67 ti,hwmods = "l3_main";
68
69 prcm: prcm@48180000 {
70 compatible = "ti,dm816-prcm";
71 reg = <0x48180000 0x4000>;
72
73 prcm_clocks: clocks {
74 #address-cells = <1>;
75 #size-cells = <0>;
76 };
77
78 prcm_clockdomains: clockdomains {
79 };
80 };
81
82 scrm: scrm@48140000 {
83 compatible = "ti,dm816-scrm", "simple-bus";
84 reg = <0x48140000 0x21000>;
85 #address-cells = <1>;
86 #size-cells = <1>;
87 ranges = <0 0x48140000 0x21000>;
88
89 dm816x_pinmux: pinmux@800 {
90 compatible = "pinctrl-single";
91 reg = <0x800 0x50a>;
92 #address-cells = <1>;
93 #size-cells = <0>;
94 pinctrl-single,register-width = <16>;
95 pinctrl-single,function-mask = <0xf>;
96 };
97
98 /* Device Configuration Registers */
99 scm_conf: syscon@600 {
67
68 prcm: prcm@48180000 {
69 compatible = "ti,dm816-prcm";
70 reg = <0x48180000 0x4000>;
71
72 prcm_clocks: clocks {
73 #address-cells = <1>;
74 #size-cells = <0>;
75 };
76
77 prcm_clockdomains: clockdomains {
78 };
79 };
80
81 scrm: scrm@48140000 {
82 compatible = "ti,dm816-scrm", "simple-bus";
83 reg = <0x48140000 0x21000>;
84 #address-cells = <1>;
85 #size-cells = <1>;
86 ranges = <0 0x48140000 0x21000>;
87
88 dm816x_pinmux: pinmux@800 {
89 compatible = "pinctrl-single";
90 reg = <0x800 0x50a>;
91 #address-cells = <1>;
92 #size-cells = <0>;
93 pinctrl-single,register-width = <16>;
94 pinctrl-single,function-mask = <0xf>;
95 };
96
97 /* Device Configuration Registers */
98 scm_conf: syscon@600 {
100 compatible = "syscon";
99 compatible = "syscon", "simple-bus";
101 reg = <0x600 0x110>;
102 #address-cells = <1>;
103 #size-cells = <1>;
100 reg = <0x600 0x110>;
101 #address-cells = <1>;
102 #size-cells = <1>;
103 ranges = <0 0x600 0x110>;
104
105 usb_phy0: usb-phy@20 {
106 compatible = "ti,dm8168-usb-phy";
107 reg = <0x20 0x8>;
108 reg-names = "phy";
109 clocks = <&main_fapll 6>;
110 clock-names = "refclk";
111 #phy-cells = <0>;
112 syscon = <&scm_conf>;
113 };
114
115 usb_phy1: usb-phy@28 {
116 compatible = "ti,dm8168-usb-phy";
117 reg = <0x28 0x8>;
118 reg-names = "phy";
119 clocks = <&main_fapll 6>;
120 clock-names = "refclk";
121 #phy-cells = <0>;
122 syscon = <&scm_conf>;
123 };
104 };
105
106 scrm_clocks: clocks {
107 #address-cells = <1>;
108 #size-cells = <0>;
109 };
110
111 scrm_clockdomains: clockdomains {
112 };
113 };
114
115 edma: edma@49000000 {
116 compatible = "ti,edma3";
117 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
118 reg = <0x49000000 0x10000>,
119 <0x44e10f90 0x40>;
120 interrupts = <12 13 14>;
121 #dma-cells = <1>;
122 };
123
124 elm: elm@48080000 {
125 compatible = "ti,816-elm";
126 ti,hwmods = "elm";
127 reg = <0x48080000 0x2000>;
128 interrupts = <4>;
129 };
130
131 gpio1: gpio@48032000 {
124 };
125
126 scrm_clocks: clocks {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 };
130
131 scrm_clockdomains: clockdomains {
132 };
133 };
134
135 edma: edma@49000000 {
136 compatible = "ti,edma3";
137 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3";
138 reg = <0x49000000 0x10000>,
139 <0x44e10f90 0x40>;
140 interrupts = <12 13 14>;
141 #dma-cells = <1>;
142 };
143
144 elm: elm@48080000 {
145 compatible = "ti,816-elm";
146 ti,hwmods = "elm";
147 reg = <0x48080000 0x2000>;
148 interrupts = <4>;
149 };
150
151 gpio1: gpio@48032000 {
132 compatible = "ti,omap3-gpio";
152 compatible = "ti,omap4-gpio";
133 ti,hwmods = "gpio1";
153 ti,hwmods = "gpio1";
154 ti,gpio-always-on;
134 reg = <0x48032000 0x1000>;
155 reg = <0x48032000 0x1000>;
135 interrupts = <97>;
156 interrupts = <96>;
157 gpio-controller;
158 #gpio-cells = <2>;
159 interrupt-controller;
160 #interrupt-cells = <2>;
136 };
137
138 gpio2: gpio@4804c000 {
161 };
162
163 gpio2: gpio@4804c000 {
139 compatible = "ti,omap3-gpio";
164 compatible = "ti,omap4-gpio";
140 ti,hwmods = "gpio2";
165 ti,hwmods = "gpio2";
166 ti,gpio-always-on;
141 reg = <0x4804c000 0x1000>;
167 reg = <0x4804c000 0x1000>;
142 interrupts = <99>;
168 interrupts = <98>;
169 gpio-controller;
170 #gpio-cells = <2>;
171 interrupt-controller;
172 #interrupt-cells = <2>;
143 };
144
145 gpmc: gpmc@50000000 {
146 compatible = "ti,am3352-gpmc";
147 ti,hwmods = "gpmc";
148 reg = <0x50000000 0x2000>;
149 #address-cells = <2>;
150 #size-cells = <1>;
151 interrupts = <100>;
173 };
174
175 gpmc: gpmc@50000000 {
176 compatible = "ti,am3352-gpmc";
177 ti,hwmods = "gpmc";
178 reg = <0x50000000 0x2000>;
179 #address-cells = <2>;
180 #size-cells = <1>;
181 interrupts = <100>;
182 dmas = <&edma 52>;
183 dma-names = "rxtx";
152 gpmc,num-cs = <6>;
153 gpmc,num-waitpins = <2>;
154 };
155
156 i2c1: i2c@48028000 {
157 compatible = "ti,omap4-i2c";
158 ti,hwmods = "i2c1";
159 reg = <0x48028000 0x1000>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 interrupts = <70>;
163 dmas = <&edma 58 &edma 59>;
164 dma-names = "tx", "rx";
165 };
166
167 i2c2: i2c@4802a000 {
168 compatible = "ti,omap4-i2c";
169 ti,hwmods = "i2c2";
170 reg = <0x4802a000 0x1000>;
171 #address-cells = <1>;
172 #size-cells = <0>;
173 interrupts = <71>;
174 dmas = <&edma 60 &edma 61>;
175 dma-names = "tx", "rx";
176 };
177
178 intc: interrupt-controller@48200000 {
179 compatible = "ti,dm816-intc";
180 interrupt-controller;
181 #interrupt-cells = <1>;
182 reg = <0x48200000 0x1000>;
183 };
184
185 mailbox: mailbox@480c8000 {
186 compatible = "ti,omap4-mailbox";
187 reg = <0x480c8000 0x2000>;
188 interrupts = <77>;
189 ti,hwmods = "mailbox";
184 gpmc,num-cs = <6>;
185 gpmc,num-waitpins = <2>;
186 };
187
188 i2c1: i2c@48028000 {
189 compatible = "ti,omap4-i2c";
190 ti,hwmods = "i2c1";
191 reg = <0x48028000 0x1000>;
192 #address-cells = <1>;
193 #size-cells = <0>;
194 interrupts = <70>;
195 dmas = <&edma 58 &edma 59>;
196 dma-names = "tx", "rx";
197 };
198
199 i2c2: i2c@4802a000 {
200 compatible = "ti,omap4-i2c";
201 ti,hwmods = "i2c2";
202 reg = <0x4802a000 0x1000>;
203 #address-cells = <1>;
204 #size-cells = <0>;
205 interrupts = <71>;
206 dmas = <&edma 60 &edma 61>;
207 dma-names = "tx", "rx";
208 };
209
210 intc: interrupt-controller@48200000 {
211 compatible = "ti,dm816-intc";
212 interrupt-controller;
213 #interrupt-cells = <1>;
214 reg = <0x48200000 0x1000>;
215 };
216
217 mailbox: mailbox@480c8000 {
218 compatible = "ti,omap4-mailbox";
219 reg = <0x480c8000 0x2000>;
220 interrupts = <77>;
221 ti,hwmods = "mailbox";
222 #mbox-cells = <1>;
190 ti,mbox-num-users = <4>;
191 ti,mbox-num-fifos = <12>;
192 mbox_dsp: mbox_dsp {
193 ti,mbox-tx = <3 0 0>;
194 ti,mbox-rx = <0 0 0>;
195 };
196 };
197
223 ti,mbox-num-users = <4>;
224 ti,mbox-num-fifos = <12>;
225 mbox_dsp: mbox_dsp {
226 ti,mbox-tx = <3 0 0>;
227 ti,mbox-rx = <0 0 0>;
228 };
229 };
230
231 spinbox: spinbox@480ca000 {
232 compatible = "ti,omap4-hwspinlock";
233 reg = <0x480ca000 0x2000>;
234 ti,hwmods = "spinbox";
235 #hwlock-cells = <1>;
236 };
237
198 mdio: mdio@4a100800 {
199 compatible = "ti,davinci_mdio";
200 #address-cells = <1>;
201 #size-cells = <0>;
202 reg = <0x4a100800 0x100>;
203 ti,hwmods = "davinci_mdio";
204 bus_freq = <1000000>;
205 phy0: ethernet-phy@0 {
206 reg = <1>;
207 };
208 phy1: ethernet-phy@1 {
209 reg = <2>;
210 };
211 };
212
213 eth0: ethernet@4a100000 {
214 compatible = "ti,dm816-emac";
215 ti,hwmods = "emac0";
216 reg = <0x4a100000 0x800
217 0x4a100900 0x3700>;
218 clocks = <&sysclk24_ck>;
219 syscon = <&scm_conf>;
220 ti,davinci-ctrl-reg-offset = <0>;
221 ti,davinci-ctrl-mod-reg-offset = <0x900>;
222 ti,davinci-ctrl-ram-offset = <0x2000>;
223 ti,davinci-ctrl-ram-size = <0x2000>;
224 interrupts = <40 41 42 43>;
225 phy-handle = <&phy0>;
226 };
227
228 eth1: ethernet@4a120000 {
229 compatible = "ti,dm816-emac";
230 ti,hwmods = "emac1";
231 reg = <0x4a120000 0x4000>;
232 clocks = <&sysclk24_ck>;
233 syscon = <&scm_conf>;
234 ti,davinci-ctrl-reg-offset = <0>;
235 ti,davinci-ctrl-mod-reg-offset = <0x900>;
236 ti,davinci-ctrl-ram-offset = <0x2000>;
237 ti,davinci-ctrl-ram-size = <0x2000>;
238 interrupts = <44 45 46 47>;
239 phy-handle = <&phy1>;
240 };
241
242 mcspi1: spi@48030000 {
243 compatible = "ti,omap4-mcspi";
244 reg = <0x48030000 0x1000>;
245 #address-cells = <1>;
246 #size-cells = <0>;
247 interrupts = <65>;
248 ti,spi-num-cs = <4>;
249 ti,hwmods = "mcspi1";
250 dmas = <&edma 16 &edma 17
238 mdio: mdio@4a100800 {
239 compatible = "ti,davinci_mdio";
240 #address-cells = <1>;
241 #size-cells = <0>;
242 reg = <0x4a100800 0x100>;
243 ti,hwmods = "davinci_mdio";
244 bus_freq = <1000000>;
245 phy0: ethernet-phy@0 {
246 reg = <1>;
247 };
248 phy1: ethernet-phy@1 {
249 reg = <2>;
250 };
251 };
252
253 eth0: ethernet@4a100000 {
254 compatible = "ti,dm816-emac";
255 ti,hwmods = "emac0";
256 reg = <0x4a100000 0x800
257 0x4a100900 0x3700>;
258 clocks = <&sysclk24_ck>;
259 syscon = <&scm_conf>;
260 ti,davinci-ctrl-reg-offset = <0>;
261 ti,davinci-ctrl-mod-reg-offset = <0x900>;
262 ti,davinci-ctrl-ram-offset = <0x2000>;
263 ti,davinci-ctrl-ram-size = <0x2000>;
264 interrupts = <40 41 42 43>;
265 phy-handle = <&phy0>;
266 };
267
268 eth1: ethernet@4a120000 {
269 compatible = "ti,dm816-emac";
270 ti,hwmods = "emac1";
271 reg = <0x4a120000 0x4000>;
272 clocks = <&sysclk24_ck>;
273 syscon = <&scm_conf>;
274 ti,davinci-ctrl-reg-offset = <0>;
275 ti,davinci-ctrl-mod-reg-offset = <0x900>;
276 ti,davinci-ctrl-ram-offset = <0x2000>;
277 ti,davinci-ctrl-ram-size = <0x2000>;
278 interrupts = <44 45 46 47>;
279 phy-handle = <&phy1>;
280 };
281
282 mcspi1: spi@48030000 {
283 compatible = "ti,omap4-mcspi";
284 reg = <0x48030000 0x1000>;
285 #address-cells = <1>;
286 #size-cells = <0>;
287 interrupts = <65>;
288 ti,spi-num-cs = <4>;
289 ti,hwmods = "mcspi1";
290 dmas = <&edma 16 &edma 17
251 &edma 18 &edma 19>;
252 dma-names = "tx0", "rx0", "tx1", "rx1";
291 &edma 18 &edma 19
292 &edma 20 &edma 21
293 &edma 22 &edma 23>;
294 dma-names = "tx0", "rx0", "tx1", "rx1",
295 "tx2", "rx2", "tx3", "rx3";
253 };
254
255 mmc1: mmc@48060000 {
256 compatible = "ti,omap4-hsmmc";
257 reg = <0x48060000 0x11000>;
258 ti,hwmods = "mmc1";
259 interrupts = <64>;
260 dmas = <&edma 24 &edma 25>;
261 dma-names = "tx", "rx";
262 };
263
264 timer1: timer@4802e000 {
265 compatible = "ti,dm816-timer";
266 reg = <0x4802e000 0x2000>;
267 interrupts = <67>;
268 ti,hwmods = "timer1";
269 ti,timer-alwon;
270 };
271
272 timer2: timer@48040000 {
273 compatible = "ti,dm816-timer";
274 reg = <0x48040000 0x2000>;
275 interrupts = <68>;
276 ti,hwmods = "timer2";
277 };
278
279 timer3: timer@48042000 {
280 compatible = "ti,dm816-timer";
281 reg = <0x48042000 0x2000>;
282 interrupts = <69>;
283 ti,hwmods = "timer3";
284 };
285
286 timer4: timer@48044000 {
287 compatible = "ti,dm816-timer";
288 reg = <0x48044000 0x2000>;
289 interrupts = <92>;
290 ti,hwmods = "timer4";
296 };
297
298 mmc1: mmc@48060000 {
299 compatible = "ti,omap4-hsmmc";
300 reg = <0x48060000 0x11000>;
301 ti,hwmods = "mmc1";
302 interrupts = <64>;
303 dmas = <&edma 24 &edma 25>;
304 dma-names = "tx", "rx";
305 };
306
307 timer1: timer@4802e000 {
308 compatible = "ti,dm816-timer";
309 reg = <0x4802e000 0x2000>;
310 interrupts = <67>;
311 ti,hwmods = "timer1";
312 ti,timer-alwon;
313 };
314
315 timer2: timer@48040000 {
316 compatible = "ti,dm816-timer";
317 reg = <0x48040000 0x2000>;
318 interrupts = <68>;
319 ti,hwmods = "timer2";
320 };
321
322 timer3: timer@48042000 {
323 compatible = "ti,dm816-timer";
324 reg = <0x48042000 0x2000>;
325 interrupts = <69>;
326 ti,hwmods = "timer3";
327 };
328
329 timer4: timer@48044000 {
330 compatible = "ti,dm816-timer";
331 reg = <0x48044000 0x2000>;
332 interrupts = <92>;
333 ti,hwmods = "timer4";
334 ti,timer-pwm;
291 };
292
293 timer5: timer@48046000 {
294 compatible = "ti,dm816-timer";
295 reg = <0x48046000 0x2000>;
296 interrupts = <93>;
297 ti,hwmods = "timer5";
335 };
336
337 timer5: timer@48046000 {
338 compatible = "ti,dm816-timer";
339 reg = <0x48046000 0x2000>;
340 interrupts = <93>;
341 ti,hwmods = "timer5";
342 ti,timer-pwm;
298 };
299
300 timer6: timer@48048000 {
301 compatible = "ti,dm816-timer";
302 reg = <0x48048000 0x2000>;
303 interrupts = <94>;
304 ti,hwmods = "timer6";
343 };
344
345 timer6: timer@48048000 {
346 compatible = "ti,dm816-timer";
347 reg = <0x48048000 0x2000>;
348 interrupts = <94>;
349 ti,hwmods = "timer6";
350 ti,timer-pwm;
305 };
306
307 timer7: timer@4804a000 {
308 compatible = "ti,dm816-timer";
309 reg = <0x4804a000 0x2000>;
310 interrupts = <95>;
311 ti,hwmods = "timer7";
351 };
352
353 timer7: timer@4804a000 {
354 compatible = "ti,dm816-timer";
355 reg = <0x4804a000 0x2000>;
356 interrupts = <95>;
357 ti,hwmods = "timer7";
358 ti,timer-pwm;
312 };
313
314 uart1: uart@48020000 {
315 compatible = "ti,omap3-uart";
316 ti,hwmods = "uart1";
317 reg = <0x48020000 0x2000>;
318 clock-frequency = <48000000>;
319 interrupts = <72>;
320 dmas = <&edma 26 &edma 27>;
321 dma-names = "tx", "rx";
322 };
323
324 uart2: uart@48022000 {
325 compatible = "ti,omap3-uart";
326 ti,hwmods = "uart2";
327 reg = <0x48022000 0x2000>;
328 clock-frequency = <48000000>;
329 interrupts = <73>;
330 dmas = <&edma 28 &edma 29>;
331 dma-names = "tx", "rx";
332 };
333
334 uart3: uart@48024000 {
335 compatible = "ti,omap3-uart";
336 ti,hwmods = "uart3";
337 reg = <0x48024000 0x2000>;
338 clock-frequency = <48000000>;
339 interrupts = <74>;
340 dmas = <&edma 30 &edma 31>;
341 dma-names = "tx", "rx";
342 };
343
344 /* NOTE: USB needs a transceiver driver for phys to work */
345 usb: usb_otg_hs@47401000 {
346 compatible = "ti,am33xx-usb";
347 reg = <0x47401000 0x400000>;
348 ranges;
349 #address-cells = <1>;
350 #size-cells = <1>;
351 ti,hwmods = "usb_otg_hs";
352
353 usb0: usb@47401000 {
359 };
360
361 uart1: uart@48020000 {
362 compatible = "ti,omap3-uart";
363 ti,hwmods = "uart1";
364 reg = <0x48020000 0x2000>;
365 clock-frequency = <48000000>;
366 interrupts = <72>;
367 dmas = <&edma 26 &edma 27>;
368 dma-names = "tx", "rx";
369 };
370
371 uart2: uart@48022000 {
372 compatible = "ti,omap3-uart";
373 ti,hwmods = "uart2";
374 reg = <0x48022000 0x2000>;
375 clock-frequency = <48000000>;
376 interrupts = <73>;
377 dmas = <&edma 28 &edma 29>;
378 dma-names = "tx", "rx";
379 };
380
381 uart3: uart@48024000 {
382 compatible = "ti,omap3-uart";
383 ti,hwmods = "uart3";
384 reg = <0x48024000 0x2000>;
385 clock-frequency = <48000000>;
386 interrupts = <74>;
387 dmas = <&edma 30 &edma 31>;
388 dma-names = "tx", "rx";
389 };
390
391 /* NOTE: USB needs a transceiver driver for phys to work */
392 usb: usb_otg_hs@47401000 {
393 compatible = "ti,am33xx-usb";
394 reg = <0x47401000 0x400000>;
395 ranges;
396 #address-cells = <1>;
397 #size-cells = <1>;
398 ti,hwmods = "usb_otg_hs";
399
400 usb0: usb@47401000 {
354 compatible = "ti,musb-am33xx";
401 compatible = "ti,musb-dm816";
355 reg = <0x47401400 0x400
356 0x47401000 0x200>;
357 reg-names = "mc", "control";
358 interrupts = <18>;
359 interrupt-names = "mc";
402 reg = <0x47401400 0x400
403 0x47401000 0x200>;
404 reg-names = "mc", "control";
405 interrupts = <18>;
406 interrupt-names = "mc";
360 dr_mode = "otg";
407 dr_mode = "host";
408 interface-type = <0>;
409 phys = <&usb_phy0>;
410 phy-names = "usb2-phy";
361 mentor,multipoint = <1>;
362 mentor,num-eps = <16>;
363 mentor,ram-bits = <12>;
364 mentor,power = <500>;
411 mentor,multipoint = <1>;
412 mentor,num-eps = <16>;
413 mentor,ram-bits = <12>;
414 mentor,power = <500>;
415
416 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
417 &cppi41dma 2 0 &cppi41dma 3 0
418 &cppi41dma 4 0 &cppi41dma 5 0
419 &cppi41dma 6 0 &cppi41dma 7 0
420 &cppi41dma 8 0 &cppi41dma 9 0
421 &cppi41dma 10 0 &cppi41dma 11 0
422 &cppi41dma 12 0 &cppi41dma 13 0
423 &cppi41dma 14 0 &cppi41dma 0 1
424 &cppi41dma 1 1 &cppi41dma 2 1
425 &cppi41dma 3 1 &cppi41dma 4 1
426 &cppi41dma 5 1 &cppi41dma 6 1
427 &cppi41dma 7 1 &cppi41dma 8 1
428 &cppi41dma 9 1 &cppi41dma 10 1
429 &cppi41dma 11 1 &cppi41dma 12 1
430 &cppi41dma 13 1 &cppi41dma 14 1>;
431 dma-names =
432 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
433 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
434 "rx14", "rx15",
435 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
436 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
437 "tx14", "tx15";
365 };
366
367 usb1: usb@47401800 {
438 };
439
440 usb1: usb@47401800 {
368 compatible = "ti,musb-am33xx";
369 status = "disabled";
441 compatible = "ti,musb-dm816";
370 reg = <0x47401c00 0x400
371 0x47401800 0x200>;
372 reg-names = "mc", "control";
373 interrupts = <19>;
374 interrupt-names = "mc";
442 reg = <0x47401c00 0x400
443 0x47401800 0x200>;
444 reg-names = "mc", "control";
445 interrupts = <19>;
446 interrupt-names = "mc";
375 dr_mode = "otg";
447 dr_mode = "host";
448 interface-type = <0>;
449 phys = <&usb_phy1>;
450 phy-names = "usb2-phy";
376 mentor,multipoint = <1>;
377 mentor,num-eps = <16>;
378 mentor,ram-bits = <12>;
379 mentor,power = <500>;
451 mentor,multipoint = <1>;
452 mentor,num-eps = <16>;
453 mentor,ram-bits = <12>;
454 mentor,power = <500>;
455
456 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
457 &cppi41dma 17 0 &cppi41dma 18 0
458 &cppi41dma 19 0 &cppi41dma 20 0
459 &cppi41dma 21 0 &cppi41dma 22 0
460 &cppi41dma 23 0 &cppi41dma 24 0
461 &cppi41dma 25 0 &cppi41dma 26 0
462 &cppi41dma 27 0 &cppi41dma 28 0
463 &cppi41dma 29 0 &cppi41dma 15 1
464 &cppi41dma 16 1 &cppi41dma 17 1
465 &cppi41dma 18 1 &cppi41dma 19 1
466 &cppi41dma 20 1 &cppi41dma 21 1
467 &cppi41dma 22 1 &cppi41dma 23 1
468 &cppi41dma 24 1 &cppi41dma 25 1
469 &cppi41dma 26 1 &cppi41dma 27 1
470 &cppi41dma 28 1 &cppi41dma 29 1>;
471 dma-names =
472 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
473 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
474 "rx14", "rx15",
475 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
476 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
477 "tx14", "tx15";
380 };
478 };
479
480 cppi41dma: dma-controller@47402000 {
481 compatible = "ti,am3359-cppi41";
482 reg = <0x47400000 0x1000
483 0x47402000 0x1000
484 0x47403000 0x1000
485 0x47404000 0x4000>;
486 reg-names = "glue", "controller", "scheduler", "queuemgr";
487 interrupts = <17>;
488 interrupt-names = "glue";
489 #dma-cells = <2>;
490 #dma-channels = <30>;
491 #dma-requests = <256>;
492 };
381 };
382
383 wd_timer2: wd_timer@480c2000 {
384 compatible = "ti,omap3-wdt";
385 ti,hwmods = "wd_timer";
386 reg = <0x480c2000 0x1000>;
387 interrupts = <0>;
388 };
389 };
390};
391
392#include "dm816x-clocks.dtsi"
493 };
494
495 wd_timer2: wd_timer@480c2000 {
496 compatible = "ti,omap3-wdt";
497 ti,hwmods = "wd_timer";
498 reg = <0x480c2000 0x1000>;
499 interrupts = <0>;
500 };
501 };
502};
503
504#include "dm816x-clocks.dtsi"