1#include <dt-bindings/interrupt-controller/arm-gic.h>
2
3#include "skeleton.dtsi"
4
5/ {
6 #address-cells = <2>;
7 #size-cells = <2>;
8 model = "Broadcom STB (bcm7445)";
--- 62 unchanged lines hidden (view full) ---
71 ranges = <0 0x00 0xf0000000 0x1000000>;
72
73 serial@40ab00 {
74 compatible = "ns16550a";
75 reg = <0x40ab00 0x20>;
76 reg-shift = <2>;
77 reg-io-width = <4>;
78 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
79 clock-frequency = <81000000>;
80 };
81
82 sun_top_ctrl: syscon@404000 {
83 compatible = "brcm,bcm7445-sun-top-ctrl",
84 "syscon";
85 reg = <0x404000 0x51c>;
86 };
87
88 hif_cpubiuctrl: syscon@3e2400 {
89 compatible = "brcm,bcm7445-hif-cpubiuctrl",
90 "syscon";
91 reg = <0x3e2400 0x5b4>;
92 };
93
94 hif_continuation: syscon@452000 {
95 compatible = "brcm,bcm7445-hif-continuation",
96 "syscon";
97 reg = <0x452000 0x100>;
98 };
99
100 irq0_intc: interrupt-controller@40a780 {
101 compatible = "brcm,bcm7120-l2-intc";
102 interrupt-parent = <&gic>;
103 #interrupt-cells = <1>;
104 reg = <0x40a780 0x8>;
105 interrupt-controller;
106 interrupts = <GIC_SPI 0x45 0x0>,
107 <GIC_SPI 0x43 0x0>;
108 brcm,int-map-mask = <0x25c>, <0x7000000>;
109 brcm,int-fwd-mask = <0x70000>;
110 };
111
112 irq0_aon_intc: interrupt-controller@417280 {
113 compatible = "brcm,bcm7120-l2-intc";
114 reg = <0x417280 0x8>;
115 interrupt-parent = <&gic>;
116 #interrupt-cells = <1>;
117 interrupt-controller;
118 interrupts = <GIC_SPI 0x46 0x0>,
119 <GIC_SPI 0x44 0x0>,
120 <GIC_SPI 0x49 0x0>;
121 brcm,int-map-mask = <0x1e3 0x18000000 0x100000>;
122 brcm,int-fwd-mask = <0x0>;
123 brcm,irq-can-wake;
124 };
125
126 hif_intr2_intc: interrupt-controller@3e1000 {
127 compatible = "brcm,l2-intc";
128 reg = <0x3e1000 0x30>;
129 interrupt-controller;
130 #interrupt-cells = <1>;
131 interrupts = <GIC_SPI 0x20 0x0>;
132 interrupt-parent = <&gic>;
133 interrupt-names = "hif";
134 };
135
136 aon_pm_l2_intc: interrupt-controller@410640 {
137 compatible = "brcm,l2-intc";
138 reg = <0x410640 0x30>;
139 interrupt-controller;
140 #interrupt-cells = <1>;
141 interrupts = <GIC_SPI 0x40 0x0>;
142 interrupt-parent = <&gic>;
143 brcm,irq-can-wake;
144 };
145
146 aon-ctrl@410000 {
147 compatible = "brcm,brcmstb-aon-ctrl";
148 reg = <0x410000 0x200>, <0x410200 0x400>;
149 reg-names = "aon-ctrl", "aon-sram";
150 };
151
152 nand: nand@3e2800 {
153 status = "disabled";
154 #address-cells = <1>;
155 #size-cells = <0>;
156 compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand";
157 reg-names = "nand", "flash-dma";
158 reg = <0x3e2800 0x600>, <0x3e3000 0x2c>;
159 interrupt-parent = <&hif_intr2_intc>;
160 interrupts = <24>, <4>;
161 interrupt-names = "nand_ctlrdy", "flash_dma_done";
162 };
163
164 sata@45a000 {
165 compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
166 reg-names = "ahci", "top-ctrl";
167 reg = <0x45a000 0xa9c>, <0x458040 0x24>;
168 interrupts = <GIC_SPI 30 0>;
169 #address-cells = <1>;
170 #size-cells = <0>;
171
172 sata0: sata-port@0 {
173 reg = <0>;
174 phys = <&sata_phy0>;
175 };
176
177 sata1: sata-port@1 {
178 reg = <1>;
179 phys = <&sata_phy1>;
180 };
181 };
182
183 sata_phy: sata-phy@458100 {
184 compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3";
185 reg = <0x458100 0x1f00>;
186 reg-names = "phy";
187 #address-cells = <0x1>;
188 #size-cells = <0x0>;
189
190 sata_phy0: sata-phy@0 {
191 reg = <0>;
192 #phy-cells = <0>;
193 };
194
195 sata_phy1: sata-phy@1 {
196 reg = <1>;
197 #phy-cells = <0>;
198 };
199 };
200
201 upg_gio: gpio@40a700 {
202 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
203 reg = <0x40a700 0x80>;
204 #gpio-cells = <2>;
205 #interrupt-cells = <2>;
206 gpio-controller;
207 interrupt-controller;
208 interrupt-parent = <&irq0_intc>;
209 interrupts = <6>;
210 brcm,gpio-bank-widths = <32 32 32 24>;
211 };
212
213 upg_gio_aon: gpio@4172c0 {
214 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
215 reg = <0x4172c0 0x40>;
216 #gpio-cells = <2>;
217 #interrupt-cells = <2>;
218 gpio-controller;
219 interrupt-controller;
220 interrupts-extended = <&irq0_aon_intc 0x6>,
221 <&aon_pm_l2_intc 0x5>;
222 wakeup-source;
223 brcm,gpio-bank-widths = <18 4>;
224 };
225
226 };
227
228 memory_controllers {
229 compatible = "simple-bus";
230 ranges = <0x0 0x0 0xf1100000 0x200000>;
231 #address-cells = <1>;
232 #size-cells = <1>;
233
234 memc@0 {
235 compatible = "brcm,brcmstb-memc", "simple-bus";
236 #address-cells = <1>;
237 #size-cells = <1>;
238 ranges = <0x0 0x0 0x80000>;
239
240 memc-ddr@2000 {
241 compatible = "brcm,brcmstb-memc-ddr";
242 reg = <0x2000 0x800>;
243 };
244
245 ddr-phy@6000 {
246 compatible = "brcm,brcmstb-ddr-phy-v240.1";
247 reg = <0x6000 0x21c>;
248 };
249
250 shimphy@8000 {
251 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
252 reg = <0x8000 0xe4>;
253 };
254 };
255
256 memc@1 {
257 compatible = "brcm,brcmstb-memc", "simple-bus";
258 #address-cells = <1>;
259 #size-cells = <1>;
260 ranges = <0x0 0x80000 0x80000>;
261
262 memc-ddr@2000 {
263 compatible = "brcm,brcmstb-memc-ddr";
264 reg = <0x2000 0x800>;
265 };
266
267 ddr-phy@6000 {
268 compatible = "brcm,brcmstb-ddr-phy-v240.1";
269 reg = <0x6000 0x21c>;
270 };
271
272 shimphy@8000 {
273 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
274 reg = <0x8000 0xe4>;
275 };
276 };
277
278 memc@2 {
279 compatible = "brcm,brcmstb-memc", "simple-bus";
280 #address-cells = <1>;
281 #size-cells = <1>;
282 ranges = <0x0 0x100000 0x80000>;
283
284 memc-ddr@2000 {
285 compatible = "brcm,brcmstb-memc-ddr";
286 reg = <0x2000 0x800>;
287 };
288
289 ddr-phy@6000 {
290 compatible = "brcm,brcmstb-ddr-phy-v240.1";
291 reg = <0x6000 0x21c>;
292 };
293
294 shimphy@8000 {
295 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
296 reg = <0x8000 0xe4>;
297 };
298 };
299 };
300
301 sram@ffe00000 {
302 compatible = "brcm,boot-sram", "mmio-sram";
303 reg = <0x0 0xffe00000 0x0 0x10000>;
304 };
305
306 smpboot {
307 compatible = "brcm,brcmstb-smpboot";
308 syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
309 syscon-cont = <&hif_continuation>;
310 };
311
312 reboot {
313 compatible = "brcm,brcmstb-reboot";
314 syscon = <&sun_top_ctrl 0x304 0x308>;
315 };
316};
2
3#include "skeleton.dtsi"
4
5/ {
6 #address-cells = <2>;
7 #size-cells = <2>;
8 model = "Broadcom STB (bcm7445)";
--- 62 unchanged lines hidden (view full) ---
71 ranges = <0 0x00 0xf0000000 0x1000000>;
72
73 serial@40ab00 {
74 compatible = "ns16550a";
75 reg = <0x40ab00 0x20>;
76 reg-shift = <2>;
77 reg-io-width = <4>;
78 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
79 clock-frequency = <81000000>;
80 };
81
82 sun_top_ctrl: syscon@404000 {
83 compatible = "brcm,bcm7445-sun-top-ctrl",
84 "syscon";
85 reg = <0x404000 0x51c>;
86 };
87
88 hif_cpubiuctrl: syscon@3e2400 {
89 compatible = "brcm,bcm7445-hif-cpubiuctrl",
90 "syscon";
91 reg = <0x3e2400 0x5b4>;
92 };
93
94 hif_continuation: syscon@452000 {
95 compatible = "brcm,bcm7445-hif-continuation",
96 "syscon";
97 reg = <0x452000 0x100>;
98 };
99
100 irq0_intc: interrupt-controller@40a780 {
101 compatible = "brcm,bcm7120-l2-intc";
102 interrupt-parent = <&gic>;
103 #interrupt-cells = <1>;
104 reg = <0x40a780 0x8>;
105 interrupt-controller;
106 interrupts = <GIC_SPI 0x45 0x0>,
107 <GIC_SPI 0x43 0x0>;
108 brcm,int-map-mask = <0x25c>, <0x7000000>;
109 brcm,int-fwd-mask = <0x70000>;
110 };
111
112 irq0_aon_intc: interrupt-controller@417280 {
113 compatible = "brcm,bcm7120-l2-intc";
114 reg = <0x417280 0x8>;
115 interrupt-parent = <&gic>;
116 #interrupt-cells = <1>;
117 interrupt-controller;
118 interrupts = <GIC_SPI 0x46 0x0>,
119 <GIC_SPI 0x44 0x0>,
120 <GIC_SPI 0x49 0x0>;
121 brcm,int-map-mask = <0x1e3 0x18000000 0x100000>;
122 brcm,int-fwd-mask = <0x0>;
123 brcm,irq-can-wake;
124 };
125
126 hif_intr2_intc: interrupt-controller@3e1000 {
127 compatible = "brcm,l2-intc";
128 reg = <0x3e1000 0x30>;
129 interrupt-controller;
130 #interrupt-cells = <1>;
131 interrupts = <GIC_SPI 0x20 0x0>;
132 interrupt-parent = <&gic>;
133 interrupt-names = "hif";
134 };
135
136 aon_pm_l2_intc: interrupt-controller@410640 {
137 compatible = "brcm,l2-intc";
138 reg = <0x410640 0x30>;
139 interrupt-controller;
140 #interrupt-cells = <1>;
141 interrupts = <GIC_SPI 0x40 0x0>;
142 interrupt-parent = <&gic>;
143 brcm,irq-can-wake;
144 };
145
146 aon-ctrl@410000 {
147 compatible = "brcm,brcmstb-aon-ctrl";
148 reg = <0x410000 0x200>, <0x410200 0x400>;
149 reg-names = "aon-ctrl", "aon-sram";
150 };
151
152 nand: nand@3e2800 {
153 status = "disabled";
154 #address-cells = <1>;
155 #size-cells = <0>;
156 compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand";
157 reg-names = "nand", "flash-dma";
158 reg = <0x3e2800 0x600>, <0x3e3000 0x2c>;
159 interrupt-parent = <&hif_intr2_intc>;
160 interrupts = <24>, <4>;
161 interrupt-names = "nand_ctlrdy", "flash_dma_done";
162 };
163
164 sata@45a000 {
165 compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
166 reg-names = "ahci", "top-ctrl";
167 reg = <0x45a000 0xa9c>, <0x458040 0x24>;
168 interrupts = <GIC_SPI 30 0>;
169 #address-cells = <1>;
170 #size-cells = <0>;
171
172 sata0: sata-port@0 {
173 reg = <0>;
174 phys = <&sata_phy0>;
175 };
176
177 sata1: sata-port@1 {
178 reg = <1>;
179 phys = <&sata_phy1>;
180 };
181 };
182
183 sata_phy: sata-phy@458100 {
184 compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3";
185 reg = <0x458100 0x1f00>;
186 reg-names = "phy";
187 #address-cells = <0x1>;
188 #size-cells = <0x0>;
189
190 sata_phy0: sata-phy@0 {
191 reg = <0>;
192 #phy-cells = <0>;
193 };
194
195 sata_phy1: sata-phy@1 {
196 reg = <1>;
197 #phy-cells = <0>;
198 };
199 };
200
201 upg_gio: gpio@40a700 {
202 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
203 reg = <0x40a700 0x80>;
204 #gpio-cells = <2>;
205 #interrupt-cells = <2>;
206 gpio-controller;
207 interrupt-controller;
208 interrupt-parent = <&irq0_intc>;
209 interrupts = <6>;
210 brcm,gpio-bank-widths = <32 32 32 24>;
211 };
212
213 upg_gio_aon: gpio@4172c0 {
214 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
215 reg = <0x4172c0 0x40>;
216 #gpio-cells = <2>;
217 #interrupt-cells = <2>;
218 gpio-controller;
219 interrupt-controller;
220 interrupts-extended = <&irq0_aon_intc 0x6>,
221 <&aon_pm_l2_intc 0x5>;
222 wakeup-source;
223 brcm,gpio-bank-widths = <18 4>;
224 };
225
226 };
227
228 memory_controllers {
229 compatible = "simple-bus";
230 ranges = <0x0 0x0 0xf1100000 0x200000>;
231 #address-cells = <1>;
232 #size-cells = <1>;
233
234 memc@0 {
235 compatible = "brcm,brcmstb-memc", "simple-bus";
236 #address-cells = <1>;
237 #size-cells = <1>;
238 ranges = <0x0 0x0 0x80000>;
239
240 memc-ddr@2000 {
241 compatible = "brcm,brcmstb-memc-ddr";
242 reg = <0x2000 0x800>;
243 };
244
245 ddr-phy@6000 {
246 compatible = "brcm,brcmstb-ddr-phy-v240.1";
247 reg = <0x6000 0x21c>;
248 };
249
250 shimphy@8000 {
251 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
252 reg = <0x8000 0xe4>;
253 };
254 };
255
256 memc@1 {
257 compatible = "brcm,brcmstb-memc", "simple-bus";
258 #address-cells = <1>;
259 #size-cells = <1>;
260 ranges = <0x0 0x80000 0x80000>;
261
262 memc-ddr@2000 {
263 compatible = "brcm,brcmstb-memc-ddr";
264 reg = <0x2000 0x800>;
265 };
266
267 ddr-phy@6000 {
268 compatible = "brcm,brcmstb-ddr-phy-v240.1";
269 reg = <0x6000 0x21c>;
270 };
271
272 shimphy@8000 {
273 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
274 reg = <0x8000 0xe4>;
275 };
276 };
277
278 memc@2 {
279 compatible = "brcm,brcmstb-memc", "simple-bus";
280 #address-cells = <1>;
281 #size-cells = <1>;
282 ranges = <0x0 0x100000 0x80000>;
283
284 memc-ddr@2000 {
285 compatible = "brcm,brcmstb-memc-ddr";
286 reg = <0x2000 0x800>;
287 };
288
289 ddr-phy@6000 {
290 compatible = "brcm,brcmstb-ddr-phy-v240.1";
291 reg = <0x6000 0x21c>;
292 };
293
294 shimphy@8000 {
295 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
296 reg = <0x8000 0xe4>;
297 };
298 };
299 };
300
301 sram@ffe00000 {
302 compatible = "brcm,boot-sram", "mmio-sram";
303 reg = <0x0 0xffe00000 0x0 0x10000>;
304 };
305
306 smpboot {
307 compatible = "brcm,brcmstb-smpboot";
308 syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
309 syscon-cont = <&hif_continuation>;
310 };
311
312 reboot {
313 compatible = "brcm,brcmstb-reboot";
314 syscon = <&sun_top_ctrl 0x304 0x308>;
315 };
316};